Comments (2)
No problem!
I will update that. Hopefully nothing else breaks 😅
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@stnolting, my bad. I didn't realise that SIM_CONFIG is kept local. I guess we can either export it in L22, or change it to your style. As you wish.
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Related Issues (20)
- [feature request] Makefile: Additional CXX_USER_FLAGS only for C++ Compilation HOT 3
- [feature request] Combining SPI and DMA HOT 8
- A question on simple testbech HOT 6
- Add AXI stream routing?!
- ASIC Processor boot conccept HOT 13
- JTAG halt request gets missed if it occures during an illegal instruction HOT 5
- Neorv32 synthesis in Design compiler HOT 8
- Not immediately halting when single-stepping into an exception
- Extra latency in the first `for` iteration HOT 15
- [bug] uart issue after #883 upd HOT 5
- VUnit simulation failure HOT 2
- Unexpected external Interrupt/ XIRQ behavior in Indirect Boot from SPI Flash HOT 8
- Latency measurement through `CSR(MCYCLE)` adds one extra cycle HOT 8
- Capture variable value in simulation HOT 10
- compilation error due to stack misalignment HOT 3
- XIP Flash: Not working as expected HOT 6
- HPM variation while using cache HOT 1
- FPU Float to signed integer HOT 1
- Support variable clock frequency in SYSINFO HOT 8
- openocd only supports Debug Module version 2 (0.13) and 3 (1.0), not 0 (dmstatus=0x0). This error might be caused by a JTAG signal issue. Try reducing the JTAG clock speed HOT 5
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