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analog-signal-interfacing-and-filtering-using-fpga-in-vhdl

Read the digitized values of an analog signal connected to ADC input on Spartan 3E board, do some digital filtering on these samples and output through the DAC on board, display both the input and output on a CRO. You can also use Pmod ADC with BASYS3 Board.

band-stacking-landsat-image

Stacking the Bands of Landsat Multi-Spectral Image to create a single TIF file

basic-projects-in-python

Some Programs for Practice in Python

cpp-basic-programs

Some basic Programs in C++

cropping-raster-based-on-roi

Cropping a Raster based on the Region of Interest (ROI)

enmap-data-preprocessing

file-folder-selection-gui-in-python

This is a simple GUI that can be used in any python program for selecting files or folders using GUI

fire-detection-from-flame-dataset

Deep Learning model implementation for Fire detection both classification and segmentation from the FLAME dataset.

ground-reflectance-to-toa-converter-using-6s

Bottom of Atmosphere Reflectance to Top of Atmosphere Simulation

helloworld

testing

image-conversions

This is the function to interpolate any image using different Interpolation technique

linear-ic-based-regulator

Linear IC based Voltage Regulator (LM317) for DC to DC conversion following the Bridge Rectifier

linux-tutorials

Things to be done in linux and problems faced by me

markdown-content

Markdown content for the www.aerobatic.io website

nc-to-tiff-stack

Program to convert a raster file in NetCdf format to TIFF format with all the bands stacked

python-basic-programs

Basic Python Problems with lists, tuples etc.

rectifier-with-capacitor-filter

Design of a Bridge Rectifier with Capacitor Filter for AC to DC Conversion

resourcesat-preprocessor

Converting the HDF Product to Georeferenced TIFF.

signed-8-bit-radix-4-booth-recoded-array-multiplier-in-vhdl

Design and Implement a signed 8-bit Radix-4 Booth Recoded Array Multiplier (All partial products are generated and added concurrently) using VHDL code. Do the structural coding using components for booth recoding. Partial products can be added using in-built operator + that would use Carry Propagate Adder resource within FPGA.

single-phase-inverter-12vdc-to-240vac-50hz

Design of a Inverter Converting 12VDC to 240V single phase AC delivering 5kVA load

spice-model-collections

All the spice model collected from different sources at a single space

sunnyiisc

Config files for my GitHub profile.

tcp-ip-basic-tasks

three-phase-inverter-12vdc-to-440vac-3ph-50hz

Design of a Inverter Converting 12VDC to 440V three phase AC delivering 5kVA load

verilog_practice_programs

This contains the programs that I have used while learning verilog.

youtube_downloader-customized

This is a simple python program to download the contents of youtube for offline access.