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bilateral_solver

Python code for the fast bilateral solver

bitonic-sorting

Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code

bsc

Bluespec Compiler (BSC)

cannyedge-hls

canny edge HLS implementation

comparch-vhdl-sysveri-cocotb

computerarch-bits-assignment

single cycle implementation

computerarchitecture-bits

computer architecture project files bits course

connectal_vc709

using connects for vc709

cv

deep-neural-network-hardware-accelerator

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

hdl

HDL libraries and projects

hdlbits

some Verilog codes

hdmi_pass_through_zyboz7-10

This is a simple design example showing how a HDMI signal can be passed through a FPGA without any type of processing on it. The Digilent Zybo Z7-10 development board has been used.

hfbs

a hardware-friendly bilateral solver

image-filter

some filters (boxfilter, fast bilateral filter, fast guided filter and permutohedral bilateral filter)

imagegit

image files

integrated_circuit_design_latex_report

lecture-slides

Lecture Slides opencl

linux

Linux kernel source tree

linux-xlnx

The official Linux kernel from Xilinx

ops-class.org-assignments

os161

ops-class.org OS/161 sources.

pc-builds

reference for pc building

petalinux-zybo-z7-10

pymutohedral_lattice

A python (numpy based) implementation of the original permutohedral lattice filtering code

resnet_notes

notes regarding resnet

sobel-filter-implementation-on-zedboard

implementation files for zed board , can be used for other image processing IP generated by HLS

sobel_filter_hls

sobel filter implementation on hls with DMA for using AXI DMA for implementation

tft-pynq

TPG test for TFT screen on PYNQ board

the_bilateral_solver