tareksaqr Goto Github PK
Name: Tarek Saqr
Type: User
Tarek Saqr's Projects
1.12-ghz_pll-design-and-verification-
A Top-Down design methodology of a PLL system, starting from system level design and system level modeling and simulation using Verilog-A, then verifying every block’s transistor level implementation using bottom-up verification and incremental integration concepts.
meeting-planner-datastructures-based-project.
A meeting planner is important to remember one's meetings and keep them organized. This project aims to implement a simple version of a meeting planner using a binary search tree.
super-heterodyne-receiver
Design and simulation of the basic components of an analog communication system using MATLAB programming. Specifically, an AM modulator and a corresponding super-heterodyne receiver are simulated using radio-station generated signals.
voting-system-implemented-by-mips-processor-16-bit-
This system is briefly allow for people in any meeting to vote for some decisions to make this voting more efficient and easy.
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