Name: Teekam Chand Khandelwal
Type: User
Bio: I am a student of m.tech in nit kkr
more on linkdin
https://www.linkedin.com/in/teekam-chand-k-1640a2155?
Location: jaipur,rajasthan,india
Teekam Chand Khandelwal's Projects
DESIGN DIGITAL CLOCK FOR 24/12 HOURS, USING TWO BLOCKS COUNTER AND BCD TOSEVEN SEGMENT. ALL CODE WRITTEN IN VERILOG.
decoder design using verilog and verified using system verilog and also perform code coverage operation using questa sim
adder and substractor both are controlled by different control signal
generator driver transection testbench classs
Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
it is the mini project in c. design of ATM machine
Using Verilog
dual clock dual port ram using verilog and system verilog
2x1 mux is verification is done using system verilog. For verification of mux all component are designed and simulated .rtl design -verilog testbench -systemverilog, tool-edaplayground and questasim
Floating Point ALU
in this respiratory cover adder and subtractor part and containing testbench and simulation waveform
Building a machine learning model for fraud detection
Gesture_Recognition
This project will help you in interfacing any analog sensors with FPGA through 8 bit I2C compatible ADC.
jtag tap_controller_fsm Verilog code
EDA Project case study
linear regression model for boombike facing issue
In this respiratory having two verification methods first have without scoreboard and monitor and second with includes all component
OpenSTA engine
Minimal is a Jekyll theme for GitHub Pages
In this repository added Python language basic example and 3-Minor Projects.
training labs and examples