tirumalnaidu Goto Github PK

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

buffets

Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

csi-nn2

An optimized neural network operator library for chips base on Xuantie CPU.

devoloper_manual

dpu-trd-zcu104

fpgadesignelements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

gemmini

Berkeley's Systolic Array Generator

hadware_convolutional-module

Hardware implementation of a configurable Convolutional Module.

hardware-multiplier-architectures

Verilog implementations of 6 different hardware multiplier architectures

hw

RTL, Cmodel, and testbench for NVDLA

maeri_bsv

MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)

nncase

Open deep learning compiler stack for Kendryte K210 AI accelerator

nvdla-sw

NVDLA SW

nvdla-sw-new

onnc-tutorial

open-gpu-kernel-modules

NVIDIA Linux open GPU kernel module source

openc910

OpenXuantie - OpenC910 Core

opencl-hls-cnn-accelerator

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

oximetry-fft

SpO2 and Heart Beat Measurement of PPG Data using Fast Fourier Transform

pipelined-mips-uvm

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

processor

rachitnigam.com

Rachit Nigam's personal website.

raytracing-oshw

A dedicated graphical processor for ray tracing

riscv-software-notes

Some notes on RISC-V

tengine

Tengine is a lite, high performance, modular inference engine for embedded device

thepbone

tirumalnaidu

tpu-mlir

Machine learning compiler based on MLIR for Sophgo TPU.

tvm_mlir_learn

tvm learn