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ams_models

arm-cpu-verilog

ARM-CPU implemented verilog

awesome-machine-learning

A curated list of awesome Machine Learning frameworks, libraries and software.

chisel3

Chisel 3: A Modern Hardware Design Language

cxlpapers

ddr4-memory-controller

ddr4memorycontroller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

design-and-verification-of-ddr3-memory-controller

The memory model was leveraged from micron.

eccexamples

Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material

fft-dit-fpga-verilog

Verilog module for calculation of FFT.

fft-python

FFT Examples in Python

fifo_systemverilog_assertion

Synchronous FIFO design & verification using systemVerilog Assertions

finance

150+ quantitative finance Python programs to help you gather, manipulate, and analyze stock market data

fractional-n-div-verilog

A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop

heterogen

We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol. Second, we show that the output of HeteroGen adheres to a precisely defined memory consistency model that

lowrisc

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

mem_ctrl

Memory Controller IP Core

mmse_dfe

This is a python implementation of jointly optimize feed-forward equlizer (FFE) and decision-feedback equalizer (DFE) tap weights

msic_0

openhbmc

Open-source high performance AXI4-based HyperRAM memory controller

opentitan_lowrisc

OpenTitan: Open source silicon root of trust

pcie-cxl-study

Note repository for studying Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL).

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

pulpino

An open-source microcontroller system based on RISC-V

python

Exercism exercises in Python.

python-project-based-learning

Curated list of project-based tutorials

reed-solomon-

This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length is of length 249 symbols and it can detect and correct upto 3 error symbols.

reed_solomon_decoder

Reed Solomon Decoder (204,188)

reedsolomon

A pure-python Reed Solomon encoder/decoder

riscv_scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog