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accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

avh-tflmicrospeech

Example: Micro speech for TensorFlow Lite

banditpam

BanditPAM C++ implementation and Python package

bi-real-net

Bi-Real Net: Enhancing the Performance of 1-bit CNNs With Improved Representational Capability and Advanced Training Algorithm. In ECCV 2018 and IJCV

bnn-pynq

Quantized Neural Networks (QNNs) on PYNQ

cfu-playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

cortex-m0

Experiment in creating an ARM Cortex-M0 SoC using only open source tools. This was just moved here from https://bitbucket.org/vahidi/arm-foss/

cortex-m0-soft-microcontroller

Soft-microcontroller implementation of an ARM Cortex-M0

cpp-cheatsheet

Modern C++ Cheatsheet

hcode

ipcore

logicnets

mileage

randomness_testsuite

This is a Python implementation of NIST's A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications

redress

riscv-chisel-book

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

soc-design-and-prototyping-research-enablement-kit

SoC design & prototyping

spi-ram-emu

SPI RAM Emulation on Pico

tensorflow-aarch64

TensorFlow wheels (whl) for aarch64 / ARMv8 / ARM64

tm-cosim

Hardware-Software Co-Simulation Framework for Tsetlin Machines

tsetlin_machine_xor_demo

tsetlinmachineviewer

usystolic-sim

A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

verilog-axis-tools

Verilog AXI stream components for FPGA implementation

yosys

Yosys Open SYnthesis Suite