Comments (6)
There is a patch in the master branch of nemequ/uarch-bench which adds Travis CI, but it fails due to an illegal instruction. I think it may need something like https://github.com/nemequ/uarch-bench/blob/0cce27819f45f790d4e4328be94fcc5e1b7dc5d4/psnip-bench-register.cpp#L20 to work.
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@nemequ - thanks!
Right, one big issue with uarch-bench at the moment is that I've completely written it without really any regard to non-AVX2 targets (roughly, Haswell or newer and Ryzen) without any consideration for platforms that don't support that instruction set. It's been also on my TODO to formalize support for instruction sets: for example, if an instruction set isn't supported on a given platform, tests that use that should be excluded on that platform.
I think the benchmark that is failing is misc/add-32
implemented as misc_add_loop32
in x86_methods.asm
which is the first test in the misc category, since it uses blsi
which is an BMI instruction (what's up with that, it makes no sense: probably it's a copy/paste error and this test was intended to test blsi
performance).
I can't tell what CPU arch the TravisCI servers are running, but it's not a recent intel based on Independent add chain 0.33
(only 3 integer ALUs), so maybe it's AMD (which doesn't have BMI until Ryzen, so almost certainly not what TravisCI has deployed).
I can create a bunch of issues to help here, e.g., outputting the instruction set extensions supported, the CPU line, etc, etc, but I think the best workaround to unblock you is to include --test-name=default/*
to only run the default test for now.
Thoughts?
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Only running some basic tests would at least provide a temporary workaround. I went ahead and added --test-name=default/*
, so the build now passes.
It looks like Xeon E5-2680 v2, but I doubt all their machines are the same, and even if they are today I assume they'll buy new servers eventually. I think the only stable solution would be run-time CPU feature detection (i.e.
, conditionally adding tests based on __builtin_cpu_supports
).
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So if you want to add Travis CI, all you need to do is sign up for it and enable it for this repo on Travis CI. Then it should start building every commit as soon as you pull in the patch from my repo.
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@nemequ - oh right, thats IvyBridge and I forgot they only had 3 integer ALUs (although they could still do 4 uops/cycle that could only happen if at least one used an EU other than the integer ALUs), so the 0.33 result makes perfect sense.
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Methinks this can be closed, unless there is something missing that I'm unaware of…
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Related Issues (20)
- register-stalls.cpp function too giant HOT 1
- Compilation fails HOT 3
- store forwarding does not have fixed latency HOT 11
- prefetch performance test for AMD CPUs? HOT 1
- ERROR: jevents failed while reading events, error -5 HOT 2
- Cycles event sometimes gets unprogrammed with --extra-events
- [Feature Request]: A directory in the repo with numbers from different architectures HOT 4
- build fails if python2 not available
- perf timer should work on non-Intel HOT 4
- how can i test the performance of the snippet of assembly provided by myself HOT 2
- build error HOT 4
- remove MINSIGSTKSZ usage HOT 3
- 4GHz was detected as 8GHz HOT 13
- dead link on wiki HOT 3
- clock detectd is not right for hybrid CPU. HOT 6
- make: *** [Makefile:131: page-info.o] Error 127 HOT 1
- No output when choosing a series of specific tasks HOT 12
- Questions about How much bandwidth does the L2 have to give, anyway? HOT 1
- Turboboost won't be disabled for isolated cores
- Issue building the package
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