Comments (2)
For reference, I began working on some contingency code that would try to persevere even with low voltage, and gave it up.
Basically, it configured the PLL to deliver the 48 MHz clock domain for the TRNG, USB, and SDIO and used the 8 MHz HSE directly as the system clock (with clock security enabled).
It also disabled the ART flash prefetch buffer and instruction and data caches.
That would be the most resilient config and would allow the MCU to run code from flash with 0 wait states and still be within all specified operating voltages.
I would have also have had to set the flash program/erase parallelism size down to 8 bits. But, really it's kind of pointless because of the microSD and USB operating voltage ranges bottoming out around 2.7-3V.
Of note is that at 8MHz, the screen refresh time is noticeably slower and thus the display code would need to be optimized.
Also, with an 8MHz system clock, you have to adjust the I2C clock speed to the touch panel to be less than around 299 KHz (and less to be safe -- AN3430 section 2.1.3 has more info on this). The errata sheet, section 2.4.3, mentions even using 88KHz in some circumstances. The touch panel still feels responsive at 88KHz.
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closing as not actionable
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Related Issues (20)
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