Comments (9)
The point of uniquification js to support VLSI flows that synthesize the Top, but not the Harness right?
If so, I wonder if moving forwards, we can enforce unique module names at the Chisel level, to avoid using sed scripts to edit .sv files.
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The point of uniquification js to support VLSI flows that synthesize the Top, but not the Harness right?
Correct. It is so that modules shared between the harness/top are unique and only top modules are synthesized.
If so, I wonder if moving forwards, we can enforce unique module names at the Chisel level, to avoid using sed scripts to edit .sv files.
This seems tricky to enforce. Also isn't this separate from this issue, no?
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This seems tricky to enforce. Also isn't this separate from this issue, no?
I'm not sure... there might be some chisel naming scope API that can prepend/append a prefix to the module names of all modules instantiated within the scope. Sounds like something that could/should exist. If it does exist, we can just wrap all the HarnessBinder instantiation within this "name scope".
If we had that... then we wouldn't need the uniquification script, and your multi-top sims would work correctly, even when a monolithic blackbox is instantiated in multiple places.
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Posted something on the gitter for this: https://matrix.to/#/!jSbgpvvpsPbLpsLZOC:matrix.org/$YW8mWMqiEN67_Q69TmeTRIUA_SN_LR1HdfyPK9JjELU?via=matrix.org&via=gitter.im&via=austin-harris.com
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Responded on Gitter echoing here: we would like to add a module prefixing API as a first class feature in Chisel but there are a few minor speedbumps. There is an existing but undocumented API via FIRRTL annotations in firtool, you can use https://github.com/llvm/circt/blob/main/docs/Dialects/FIRRTL/FIRRTLAnnotations.md#nestedprefixmodulesannotation.
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Thanks. I'll mess around with it and see if it works nicely for our use case. Thanks again
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I would be interested in this as well if you get something working @abejgonzalez
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For the record, I added the annotation here:
Line 147 in 8b6adb1
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