How can I generate a reset_vector io at DigitalTop module?

[csgxiong]

How can I generate a reset_vector io at DigitalTop module?

[Kevin99214]

I had to create this snippet in chipyard.IOBinders and added it to AbstractConfig to be able to pull it out to the DigitalTop level. Hope this helps!

class WithExternalResetVectorPunchthrough extends OverrideIOBinder({
  (system: HasTilesModuleImp) => {
    val io_rst_vector_pins_temp = system.reset_vector.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"rv_$i") }
    (io_rst_vector_pins_temp zip system.reset_vector).map { case (io, sysio) =>
      sysio := io 
    }
    (io_rst_vector_pins_temp, Nil)
  }
})

[cygwin24]

@csgxiong
Yes.
I have also faced the same problem with this. Because You cannot make the separate Punchthrough for both in IOBinder.
You have to add both the functionality of reset-vector and hart_ID in the same punchThrough otherwise it will override the one.

I have used this snippet

class WithExternalHartAndResetVectorPunchthrough extends OverrideIOBinder({
  (system: HasTilesModuleImp) => {
    val ports = system.tile_hartids.zipWithIndex.map { case (eio, i) => {
      IO(eio.cloneType).suggestName(s"hart_id_$i")} }
        (ports zip system.tile_hartids).map { case (io1, sysio1) =>{
        sysio1 := io1 
        }
   }

    val io_rst_vector_pins_temp = system.reset_vector.zipWithIndex.map { case (dio, i) => {
      IO(dio.cloneType).suggestName(s"reset_vector_$i")} }
        (io_rst_vector_pins_temp zip system.reset_vector).map { case (io, sysio) => { 
         sysio := io 
        }
  }
    val mylist = io_rst_vector_pins_temp :++ ports
    (mylist.toSeq, Nil)
  }
})

But this will generating the port in DigitalTop nicely. But in Chiptop it is showing the wrong polarity.
If you know how to do it correctly then let me know.

[csgxiong]

@Kevin99214
Thank you for your reply. I really appreciate it.
I had tried your ways, but it does not work. I am using chipyard V1.10 and the "make verilog CONFIG=RocketConfig" command to generate RTL .
Are there other steps need to be done after adding WithExternalResetVectorPunchthrough Config to AbstractConfig?

[Kevin99214]

Just to make sure but did you set this to true?
case SubsystemExternalResetVectorKey => true

[csgxiong]

It is My mistake.
Now when I set SubsystemExternalResetVectorKey to be true, the generator shows an exception:
Diplomacy has detected a problem with your graph:
The following node node has 1 inward connections and no outward connections.At least one outward connection was required.
1 inward nodes bound:[once-system.bootROMResetVectorSourceNode]
0 outward nodes bound:[]

[csgxiong]

When I deleted all the bootrom related configs (withbootrom/withbootaddrReg/withcustombootpin), and set SubsystemExternalResetVectorKey to be true, it finally worked.But it seems there are too mange changes.
Any ideas about it?
Thanks!

[Kevin99214]

As far as I know, the bootrom needs a reset vector register to program as part of its boot code. If you want an external reset vector, that removes the register the bootrom needs and caused the error. (anyone please correct me if I'm wrong)

For my use case, I rather boot from the address I set using the external reset vector over the bootrom so removing those bootrom configs make sense. But that'll may be different for you. It's up to you to decide if this is what you want.

[jerryz123]

Setting the defaultBootAddress of BootAddrRegParams will make the bootrom jump to a different start address.

https://github.com/ucb-bar/testchipip/blob/60a1c15f963222331b8e4127b0ece0ea210786aa/src/main/scala/boot/Configs.scala#L17-L20

[csgxiong]

@Kevin99214
Yes. What I want to do is exactly using the external reset vector to boot the cores.
Thank you for your reply.

[csgxiong]

@jerryz123
Thank you, Jerry.
I will give it a try.

[cygwin24]

@csgxiong
I also wanted to take out the reset vector out of the chiptop file. I have made the case class in BaseConfig.scala file and they try to invoke it from BaseConfig via AbstractConfig class. like

case object WithExternalResetVectorPort extends Config(
  (site, here, up) => {
    case SubsystemExternalResetVectorKey => true
  }
)

I got the same error like

parents: broadcast/system/chiptop0
locator:  (BundleBridge.scala:197:31)

1 inward nodes bound: [once-system.bootROMResetVectorSourceNode]
0 outward nodes bound: []

number of known := bindings to inward nodes: 1
number of known := bindings to outward nodes: 0
number of binding queries from inward nodes: 0
number of binding queries from outward nodes: 0

How did you solve this error ? I saw in comment section you solved this error.

[csgxiong]

@ashutgupta28
Just like what I had mented before.

When I deleted all the bootrom related configs (withbootrom/withbootaddrReg/withcustombootpin), and set SubsystemExternalResetVectorKey to be true, it finally worked.

[csgxiong]

@ashutgupta28
Ok, it seems to be a good way.
I will give it a try later.

[cygwin24]

@csgxiong
Ok. can you tell me the exact changes you have done it for taken the external reset vector out. So that I can give a try. :-)

[csgxiong]

@ashutgupta28
My steps are:
1.Delete "case BootROMLocated ***" at BaseSubsytemConfig
2.Delete "WithBootROM" + "WithCustomBootPin " + "WithBootAddrReg"+ "WithCustomBootPinPlusArg" at AbstractConfig
Then it will work!

[cygwin24]

@csgxiong
I did the same steps as you mentioned and the RTL is generating but I want to ask you did any top level reset vector port was generating in Digital Top file in your case?

[csgxiong]

@ashutgupta28
Yes.
After doing the steps, there was a reset_vector_0 port at my DigitalTop.

[csgxiong]

@ashutgupta28
Nice!!
Well, I find there is a little difference between our work.
I was using the default RocketConfig.
It maybe the reasion before.

[cygwin24]

@csgxiong
So what ever the RTL it is generating in Frontend.v file that worked in RocketConfig ? Right.. In your case
If that worked there then I assumed that it will also worked here also ..

[cygwin24]

@csgxiong
I have successfully achieved the reset vector and HartID out of the digitalTop Module. And it is fine .

But in Chiptop module it is generating as the output and internally driving as zero.
Any idea how can I change the port as output to input in Chiptop.

[csgxiong]

@ashutgupta28

@csgxiong I have successfully achieved the reset vector and HartID out of the digitalTop Module. And it is fine .

But in Chiptop module it is generating as the output and internally driving as zero. Any idea how can I change the port as output to input in Chiptop.

Hi!
When I try to pull hart_id out of the digitalTop Module, the reset vector will disapear.
How did you achieve this?

[csgxiong]

@ashutgupta28
Thank you.
That's a good one.
I will give it a try. And if there is anything new, I will keep updating.