Comments (3)
@seldridge @chick @ucbjrl @azidar @jackkoenig since you were all part of that discussion
from chiseltest.
I think this is a good summary. I am open to any approach that brings this capability to the stack. I'd like to add that there be a diagnostic interface, .i.e. a way to get the relevant Stage to report what options are in play and where they are coming from.
from chiseltest.
I see test configuration management as out of scope for chiseltest
. Users should be able to create their own solutions on top of the testing APIs that we provide.
from chiseltest.
Related Issues (20)
- Feature request: Always advance clock by one cycle at the end of failed tests HOT 6
- Does VcsBackendAnnotation support vcs Q-2020.03-SP2? HOT 1
- Can't find field of aggregate Memory in nested Module HOT 5
- FlatIO is not supported
- Feature request: Extend DecoupledDriver with Enqueue/DequeueEmpty HOT 6
- verilator: broken support for Verilog $time system task HOT 5
- FACING SAME ERROR IN DOING SIMPLE ADDITION IN CHISEL HOT 4
- Loop Query
- Chiseltest fails with None.get on zero-width literal HOT 2
- A typo in Verilator.scala HOT 1
- memory leak? HOT 5
- Chisel formal needs simple examples (README)
- No Reset Signal for DUT in Chisel Formal HOT 3
- Working Verilator Version HOT 4
- Synchronization Issues in IPCSimulatorContext
- TestApplicationException can be exposed to user but is private
- Fsdb annotation method needs to be update
- Regression with FixedPoint poke in 0.5.1+ HOT 2
- Chiseltest supports stdin at runtime? HOT 1
- any way seperate compile and simulation HOT 2
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