Comments (3)
I have viewed the second bullet point as the critical problem and path to a solution. Chisel intermixes specification (IO) and implementation (module internals) whereas other languages opt to make this explicit (VHDL has specification/implementation). Because of this, it's difficult in Chisel to think about abstracting over implementations.
I've used the following recently as something towards this:
/** A [[Module]] mixin that exposes the type of the underlying IO
* @tparam A the type of the [[Module]]'s IO
*/
trait Spec[A <: Record] { this: Module =>
override val io: A
}
I was then able to write tests for any Module with Spec[A]
. However, there then needs to be some means to convert between different module types and blackboxes. A typeclass interface object pattern worked here with toLegacy
and toBlackBox
methods.
This is likely related to programmatic IO discoverability.
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Related: #2
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I think this is out of scope right now.
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Related Issues (20)
- FACING SAME ERROR IN DOING SIMPLE ADDITION IN CHISEL HOT 4
- Loop Query
- Chiseltest fails with None.get on zero-width literal HOT 2
- A typo in Verilator.scala HOT 1
- memory leak? HOT 5
- Chisel formal needs simple examples (README)
- No Reset Signal for DUT in Chisel Formal HOT 3
- Working Verilator Version HOT 4
- Synchronization Issues in IPCSimulatorContext
- TestApplicationException can be exposed to user but is private
- Fsdb annotation method needs to be update
- Regression with FixedPoint poke in 0.5.1+ HOT 2
- Chiseltest supports stdin at runtime? HOT 1
- any way seperate compile and simulation HOT 2
- Function loadMemoryFromFile failed in chiseltest HOT 2
- chiseltest recognisez $finish in verilog fails
- Confusing Fork-Join Usage HOT 2
- Confused by fork.withRegion(Monitor) HOT 1
- TODO: implement plusarg intrinsic support for all supported simulators and formal verification
- scala.NotImplementedError: TODO: convert InlineAnnotation(ModuleName(<omitted>)) HOT 12
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