Comments (4)
So under the current single-clock semantics, such a counter is fairly straightforward, but under multiclock semantics with some notion of simulator time, it might become less clear.
For those, I was thinking:
- Probably have a way to inspect simulator time, defined in seconds
- Maybe have a way to count rising edges of clocks since the beginning of simulation, though this will need a treadle API (@chick ?) since not all clocks are necessarily under the user's control and testers2 may not be able to track everything. Note that we currently only track clocks that we know about (threads are blocked on), so rising-edges-since-beginning-of-simulation, while intuitive, might not be practical to implement. An alternative might be to have a ClockCounter / etc construct that you declare, and it tracks the number of rising edges since instantiation, but it'd be another special construct...
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Seems like the best way would be a per-clock API/object instantiated by the user...
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Yes, just per clock should do it. Something like: dut.clock().ticks()
from chiseltest.
Continue the discussion here: about ticks under reset: start counting after reset is released. Just like you would have a hardware counter:
cnt = RegInit(0.U(32.W))
cnt := cnt + 1.U
That's what I do as workaround.
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Related Issues (20)
- Feature request: Extend DecoupledDriver with Enqueue/DequeueEmpty HOT 6
- verilator: broken support for Verilog $time system task HOT 5
- FACING SAME ERROR IN DOING SIMPLE ADDITION IN CHISEL HOT 4
- Loop Query
- Chiseltest fails with None.get on zero-width literal HOT 2
- A typo in Verilator.scala HOT 1
- memory leak? HOT 5
- Chisel formal needs simple examples (README)
- No Reset Signal for DUT in Chisel Formal HOT 3
- Working Verilator Version HOT 4
- Synchronization Issues in IPCSimulatorContext
- TestApplicationException can be exposed to user but is private
- Fsdb annotation method needs to be update
- Regression with FixedPoint poke in 0.5.1+ HOT 2
- Chiseltest supports stdin at runtime? HOT 1
- any way seperate compile and simulation HOT 2
- Function loadMemoryFromFile failed in chiseltest HOT 2
- chiseltest recognisez $finish in verilog fails
- Confusing Fork-Join Usage HOT 2
- Confused by fork.withRegion(Monitor) HOT 1
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