virtual-labs/exp-half-full-adder-iitr

This experiment belongs to Digital Electronics IITR Lab.​​​​                                                 Full Name: "Construction of half and full adder using XOR and NAND gates and verification of its operation"

Introduction (Round 0)

Discipline	Engineering
Lab	Digital Electronics
Experiment	2. Construction of half/ full adder using XOR and NAND gates and verification of its operation.

About the Experiment :

This experiment is to verify the truth table of half adder and full adder by using XOR and NAND gates respectively and analyse the working of half adder and full adder circuit with the help of LEDs in simulator 1 and verify the truth table only of half adder and full adder in simulator 2.

Name of Developer	R.S. Anand
Institute	IIT Roorkee
Email id	[email protected]
Department	Electrical Engineering

Contributors List

SrNo	Name	Faculty or Student	Department	Institute	Email id
1	R.S. Anand	Faculty	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]
2	Jasbir Singh	Research Fellow	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]
3	Rajeev Kumar	Research Fellow	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]
4	Priyanshi Agarwal	Research Fellow	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]