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Wageesha Sarith Gunasena's Projects

5-staged-mips-pipeline icon 5-staged-mips-pipeline

this software is part of main project in Computer Architecture Laboratory which has been held in University of Tehran. for developing this project, i have used verilog Language in modelsim software. this project has been constructed, according to 5 staged MIPS pipeline (i.e. DesignSheet.jpg which included in the Design folder). the instruction set length of this project is 16 bit. the ALU of this Mips pipeline can do operation in Instruction Set of Type: R-Type Instruction set(register type: NOP, ADD, SUB, AND, OR, XOR, SL, SR, SRU, MUL) and I-Type Instruction set(Imediate Type: ADDI, LD, ST, BZ, JMP).

arm7 icon arm7

Implemetation of pipelined ARM7TDMI processor in Verilog

computer-science icon computer-science

:mortar_board: Path to a free self-taught education in Computer Science!

imas icon imas

University Of Peradeniya, Hackers' club image analytic server

iot-vehicle-monitoring-system icon iot-vehicle-monitoring-system

This was a project that monitoring the vehicles by using image processing that arrive and depart from construction site. Using load sensors it measure the weight and all details are uploaded to the database. there is a web site to show all details.

iot_exm_authentication_system icon iot_exm_authentication_system

This is an Arduino based device to authenticate and mark attendance of students in exams using finger prints and magnetic ID cards.

md5 icon md5

C implementation of the MD5 algorithm

mips32r1_xum icon mips32r1_xum

A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. (Old University of Utah XUM archive)

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