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8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

chatgpt-midjourney

🍭 一键拥有你自己的 ChatGPT+Midjourney 网页服务 | Own your own ChatGPT+Midjourney web service with one click

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

cplusplusthings

C++那些事

cpu

A very primitive but hopefully self-educational CPU in Verilog

cpu-1

Verilog实现的简单五级流水线CPU，开发平台：Nexys3

csdngreener

《专 业 团 队》🕺🏿 🕺🏿 🕺🏿 🕺🏿 ⚰️🕺🏿 🕺🏿 🕺🏿 🕺🏿 | 专治 CSDN 广告与各种灵魂打击 | 🐵 油猴脚本 | TamperMonkey | Chrome | FireFox | CSDN 页面浮窗广告完全过滤净化 | 国服最强 CSDN 绿化脚本

ddr3_controller

examples-in-book-write-your-own-cpu

《自己动手写CPU》一书附带的文件

integrated_circuits_and_semiconductor

Integrated_Circuits_and_Semiconductor 集成电路设计与半导体物理器件书籍

mips-cpu

MIPS CPU implemented in Verilog

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

soc-design-ddr3-controller

DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog

step_into_mips

一步一步写MIPS CPU

telegram-chinese-groups

Telegram 中文群组列表

time-series-transformers-review

A professionally curated list of awesome resources (paper, code, data, etc.) on transformers in time series.

trafficmonitor

这是一个用于显示当前网速、CPU及内存利用率的桌面悬浮窗软件，并支持任务栏显示，支持更换皮肤。

transformer-xl

tree-core-ide

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

verilog-practice

HDLBits website practices & solutions

yydz

丁真宇宙，一眼丁真合集，已有两千多张图片。The YYDZ (Yi Yan Ding Zhen / One Eye Ding Zhen) dataset.

zoomplot-matlab

MATLAB Code for Interactive Magnification of Customized Regions.