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book

Computer Networks: A Systems Approach -- Textbook

child_safety

project for UW EE542

cores-swerv-eh2

cs-notes

:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计

cse414

cse414

cse451

CSE 451: Introduction to Operating Systems (taught by Ed Lazowska)

cse550

CSE550: Systems for All

cse550-a1

cse5500

cse5501

Repo for CSE550

ddr4memorycontroller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

digital_video_introduction

A hands-on introduction to video technology: image, video, codec (av1, vp9, h265) and more (ffmpeg encoding).

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

ee562

EE 562 (Autumn 2020): Artificial Intelligence for Engineers

eh2_core

EH2: RSIC-V processor from Western Digital

fullstack-tutorial

🚀 fullstack tutorial 2022，后台技术栈/架构师之路/全栈开发社区，春招/秋招/校招/面试

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

isp_asic

RTL for ISP

litedram

Small footprint and configurable DRAM core

lm-riscv-dv

An Open-Source Design and Verification Environment for RISC-V

neurips2023-one-fits-all

The official code for "One Fits All: Power General Time Series Analysis by Pretrained LM (NeurIPS 2023 Spotlight)"

risc-v_cpu

This is digital IC design project for UW EE525

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-dv

Random instruction generator for RISC-V processor verification

rvv-intrinsic-doc

ssrl_work

work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework

summer2023-internships

Collection of Summer 2023 tech internships!

verilator

Verilator open-source SystemVerilog simulator and lint system