Comments (1)
Fixed in 85f1854, MMU traps are now executed precisely for prefetched instructions.
from w11.
Related Issues (20)
- CPU: several deficits in trap logic HOT 2
- CPU: src+dst deltas summed in mmr1 if register identical
- CPU: The AIB bit in MMU PDR register set independant of ACF field
- CPU: MMR0 trap bit set when access aborted
- CPU: no mmu trap when instruction which clears trap enable itself causes a trap HOT 1
- RK11: write protect action too slow
- migrate from Travis to GitHub actions HOT 2
- SimH scmd files fail on current 4.* version; only 3.* supported HOT 5
- time tbrun does not report correct CPU time
- asm-11 compiles nnn(pc) as nnn
- MMU: PDR A bit is set for every access
- MMU: ACF=1 traps on any access
- MMU: D space used instead of I space for PC deferred specifiers
- PSW changed after MMU aborts in dstw flows
- I have an ARTY S7 board, I'd like to try your w11 code. HOT 10
- add external ram support on basys3 Implementation HOT 3
- DZ11: modem control not implemented in backend
- DEUNA: buffer chaining not implemened in backend HOT 1
- A
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from w11.