why250's Projects
This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"
EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
Games: Create interesting games by pure python.
A series of Jupyter notebooks that walk you through the fundamentals of Machine Learning and Deep Learning in Python using Scikit-Learn, Keras and TensorFlow 2.
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
Jupyter notebooks for teaching/learning Python 3
The Missing Semester of Your CS Education 📚
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Materials and IPython notebooks for "Python for Data Analysis" by Wes McKinney, published by O'Reilly Media
Python Basics: A Practical Introduction to Python 3
Online resources for Python Crash Course, 3rd edition, from No Starch Press.
Config files for my GitHub profile.