wlduan,github

asic_backend_design_sp22

ASIC Back-end Design Flow

caravel_user_project

https://caravel-user-project.readthedocs.io

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cpu_riscv

RISCV CPU core

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cv32e40p_verif

Functional verification project for the CORE-V family of RISC-V cores.

dac-2020-tutorial

Material for OpenROAD Tutorial at DAC 2020

epc-gen2-rfid-tag-baseband-processor

Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers

floonoc

A Fast, Low-Overhead On-chip Network

g2c1messages

Generate and parse Gen2 Class1 UHF RFID reader messages at different levels

mflowgen

mflowgen -- A Modular ASIC/FPGA Flow Generator

myhdl_lib

A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.

nocgen

NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers

open_regmodel

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

rfid-verilog

RFID tag and tester in Verilog

veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

veriutils

Verification Utilities for MyHDL

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