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analog-design-of-asynchronous-sar-adc

This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

communication_system_simulation

cpp_houjie

侯捷C++课程PPT及代码,动手学起来

cs-notes

:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++

deep-ctr-prediction

CTR prediction models based on deep learning(基于深度学习的广告推荐CTR预估模型)

deepctr

Easy-to-use,Modular and Extendible package of deep-learning based CTR models.

deepctr-torch

【PyTorch】Easy-to-use,Modular and Extendible package of deep-learning based CTR models.

digital-calibration-of-sar-adc

Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)

ehcf

This is our implementation of EHCF: Efficient Heterogeneous Collaborative Filtering (AAAI 2020)

math-physics

高等数学、线性代数、概率论与数理统计、离散数学、大学物理、数字电路与逻辑设计

ml_cia

公众号: 机器学习荐货情报局 所有代码

modeling-of-10-bit-pipeline-adc-and-10-bit-dac

This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

paperlist-for-recommender-systems

Recommender Systems Paperlist that I am interested in

personal_recommendation

个性化推荐代码--初学者

reflection_summary

算法理论基础知识应知应会

tencent_social_ads

第一届腾讯社交广告高校算法大赛(决赛14名)

vscode-verilog-hdl-support

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code