y-bobo Goto Github PK

32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

amba_axi_ahb_apb

AMBA bus lecture material

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

basic_verilog

Must-have verilog systemverilog modules

bin2coe

Binary data to Xilinx COE BRAM Converter

busybear-linux

busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.

cache-replacement-algorithm-simulator

Simulator similar to Champ sim which gives then hit ratio of a given algorithm with respect to a trace file

campusshame

互联网仍有记忆！那些曾经在校招过程中毁过口头offer、意向书、三方的公司！纵然人微言轻，也想尽绵薄之力！

carrv.github.io

Workshop on Computer Architecture Research with RISC-V (CARRV)

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

clash_for_windows_pkg

A Windows/macOS GUI based on Clash

cores-swerv

SweRV EH1 core

cores-verilog

Various HDL (Verilog) IP Cores

cuassembler

An unofficial cuda assembler, for all generations of SASS, hopefully ：）

cupbop

A framework that support executing unmodified CUDA source code on non-NVIDIA devices.

deeplearningsystem

Deep Learning System core principles introduction.

ffjpeg

a simple jpeg codec.

gpgpu-sim_distribution

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

gpgpu-sim_simulations

A repository that compliments gpgpu-sim, providing automated regression scripts, simulation launching utilities and the code + arguments for simulations that complete in a reasonable amount of time on GPGPU-Sim.

home

为推广RISC-V尽些薄力

ispass2009-benchmarks

Benchmarks used in the gpgpu-sim ispass 2009 paper

kami

Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MIT

kepleras

An Open Source Kepler GPU Assembler

keystone

Keystone Enclave (QEMU + HiFive Unleashed)

language-verilog

Verilog language support in Atom

llvm

maxas

Assembler for NVIDIA Maxwell architecture

multi2sim

Multi2Sim source code

nexys-video-microblaze-ov5640-hdmi

nf5

A simple 5-stage Pipeline RISC-V core