yash-jangra Goto Github PK

-a-32-bit-5-stage-pipelined-mips-based-risc-core-based-on-harvard-architecture-

This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation

8bit_synchronous_fifo_design

Verilog implementation of an 8-bit Synchronous FIFO (First-In-First-Out) memory module

anddev

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

bare-metal-programming-guide

A bare metal programming guide (ARM microcontrollers)

completedevlopment

CompleteDevlopment

ecryption-decryption-system

Encryption Decryption System using Linear Feedback Shift Register

ee2230_digital_logic_design

groupme-gallery-dump

Dumps all images from a GroupMe chat.

hacktoberfest

This repo is my personal project for showcasing my photographs that I click and edit.

hexadecimal-keypad-scanner-in-verilog

Keypad scanners are used to enter data manually in digital telephones, computer keyboards and other digital systems. Telephones have a decimal keypad, and computer keyboards usually have a hexadecimal keypad. A keypad scanner responds to a pressed key and forms a code that uniquely identifies the key that is pressed.

hexadecimal-keypad-scanner-using-verilog

Hexadecimal Keypad Scanner and Encoder is used to detect and encode a pressed key

lbist

projects

stm32cubef4

STM32Cube MCU Full Package for the STM32F4 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits))

student_dev

team-razor-crest

Solution submission for Round-1 of the Tryst Autobot Challenge

yash-jangra

Config files for my GitHub profile.