ytdcl Goto Github PK

8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

ca-lab-all

体系结构mips-cpu实验

cpu-riscv

ACM Class 2017 Computer Architecture

get-away-now

Get away from UCAS!!!

ics-pa

The wrapper repo for NJU ICS PA.

mips_5pipelines_cpu

use chisel to complete 5 pipelines mips_cpu

nju-ics-pa2020_fall

2020年秋季南京大学 计算机系统基础 课程大作业 x86 emulator——NEMU，implemented all functions.

nscscc-mips-cpu

nutshell

RISC-V SoC designed by students in UCAS

risc-v-32i

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

risc-v-cpu

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

riscv_cpu

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

undergraduate_course_materials

Undergraduate Course Materials in UCAS, from 2017 to 2021

ustc-rvsoc

FPGA-based RISC-V CPU+SoC.