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basic_verilog

Must-have verilog systemverilog modules

csi2rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

dsitx

MIPI DSI transmitter core for Xilinx FPGAs (work in progress)

fusesoc

FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

gowinddr3_axi4_spinalhdl

Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现

hackster

Files used with hackster examples

hvhdl_fixed_point

VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

oh

Silicon proven Verilog library for IC and FPGA designers

pp4fpgas-cn

中文版 Parallel Programming for FPGAs

pp4fpgas-cn-hls

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

pynq-z2-projects

pynq-z2project

PYNQ-Z2工程

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

sdram-controller

Verilog SDRAM memory controller

spinaltemplatesbt

A basic SpinalHDL project

thinkdsp

Think DSP: Digital Signal Processing in Python, by Allen B. Downey.

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

verilog-axi

Verilog AXI components

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components

verilog_pal

PAL时序的Verilog实现

zhangjialiang-tt.github.io