zhuzhengchao Goto Github PK

2017_boe_dsi_bridge

adventures-in-ml-code

This repository holds all the code for the site http://www.adventuresinmachinelearning.com

berkeley-hardfloat

book

图书，存放在这里，权当是个云盘。

books

无它术，唯勤读书而多为之，自工

caffe

Caffe: a fast open framework for deep learning.

doc

Documentation for NVDLA.

drawio-desktop

Official electron build of draw.io

fpu

synthesiseable ieee 754 floating point library in verilog

fuchsia

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gem5-gpu

grate

Grate: Open source Tegra2+ 2D/3D user-space

hdr-plus

HDR+ Implementation

hello-world

hw

RTL, Cmodel, and testbench for NVDLA

la-core

Linear algebra accelerators for RISC-V (published in ICCD 17)

learning_gem5

Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.

learnviorb

life

magenta

Magenta Kernel, Core Drivers, and Services

neural-networks-on-silicon

This is a collection of works on neural networks and neural accelerators.

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

riscv-fpu

Basic floating-point components for RISC-V processors

riscv-isa-manual

RISC-V Instruction Set Manual

rocc-template

rocket

Rocket Microarchitectural Implementation of RISC-V ISA

rocket-chip

Rocket Chip Generator

sw

NVDLA SW