make error at the top

[zone-min]

make error at the top

[ZipCPU]

The problem traces to an update in Verilator that now requires all builds to include verilated_threads.cpp and -lpthread. Should now be fixed.

[zone-min]

Thanks, I have already fixed that .

In addtion, I'm wondering if this dbgbus is similar to the functionality of vivado's ILA ?

Best Regards!

[ZipCPU]

It can be used as part of a replacement to Vivado's ILA, yes. To do that, place a WBSCOPE on the bus for the debugging bus to access, and then you have something like ILA. The trick is ... the bus has to work perfectly for this to work. As a bonus, you can also load RAM/FLASH, configure peripherals, experiment with your design, and more. Indeed, I do this often when debugging items on an FPGA: 1) get the bus up and running, 2) measure what's going on within, 3) command a peripheral to do (something), 4) trigger a trace as that command runs, 5) go back and view the results of that trace, 6) ponder what just happened, 7) measure (again), and repeat. I should point out, not only do I use the WBSCOPE, but I've often been known to bring various state bits back as well--just to make sure components of the design properly return to IDLE before issuing the next command. (A classic component that might not? I2C. Make one little mistake, and ... the controller will need help resetting.)

[zone-min]

I got it, very appreciate for your patiently answer!