- Implemented a 32-bit multistage RISC-V processor core using Verilog HDL.
- Individually created modules like Instruction Fetc Units, Registers, Memory, ALU, Decoder of a processor.
- Integrated these Individual modules to form a single working processor core.
- Tools Used : iVerilog (version 11.0) , GTKWave
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View Code? Open in Web Editor NEWThis is an implamentation of a 32 bit RISC-V processor using Verilog HDL.