This project involves the design of a two-stage operational amplifier at 180nm technology using the GM over Id methodology. The amplifier is designed to meet the specifications: Gain > 60dB, load capacitance Cl = 20fF, gain bandwidth product (GBW) = 1GHz, and Phase margin > 50 degrees.
Specification | Value |
---|---|
Gain | > 60dB |
Load Capacitance (Cl) | 20fF |
GBW | 1GHz |
Phase Margin | > 50Β° |
- Model File: CMOS180nm
- Design Methodology: gm over ID methodology (Emphasis on optimized W/L ratio and Width/Length multiples of 0.18nm)
Before designing, the following steps were taken:
- Used Analog Designer Toolbox (ADT) for generating parameter charts using the CMOS180.txt model file.
- ADT allows plotting various parameter charts for NMOS and PMOS devices, considering different specifications such as length, VDS, VSB, etc.
- LTspice: Schematic and simulation purposes
- ADT (Analog Designer Toolbox): Generating lookup tables for CMOS 180nm and parameter charts for GM over Id methodology
- Electric Binary Software: Layout design
- Gain = 40 , "CL" =20f , Rout = 93 KΞ© (Assumed after Back Calculations)
- Let πΊπ= πΊπππ/π ππ’π‘ = 0.43mS
- Taking πΊπ/πΌπ=12, Id = 0.43ππ/12 = 35.83uA
- For NMOS: (From Look Up Tables in ADT)
- For πΊπ/πΌπ=12, πΊπ/πΊππ =77.05, πΌπ/π=9.913 , Vgs=0.7316
- Hence, Gds= 0.43ππ/77.05 = 5.58uS W= 35.83π’/9.913 =3.6u and Vg =0.7316+0.45
- and Vg = 1.18
- For PMOS:
- As, Rout = Ro(NMOS) || Ro(PMOS) Gds(PMOS)= 1/π πππ - Gds(NMOS)
- Hence , GDS(PMOS)= 5.172uS
- Now, as the current will remain the same i.e 35.83uA
- πΌπ/(πΊππ (ππππ))= 35.83π’/5.17π’=6.93 using this From LUT in ADT(Analog Designer Toolbox), Gm/Id is calculated for PMOS
- Hence , πΊπ/πΌπ=5.487 Gm (PMOS) = 5.487 * 35.83uA = 0.196mS
- For, πΊπ/πΌπ=5.487 πΌπ/π=10.8 Vsg=0.781
- Hence, W= 35.83π’/10.8 = 3.317 (Taken 3.24u)
- And Vb = 1.8 β 0.781 = 1.019
- AS CL=20f, BW (-3dB) = πΊπ/(2ππ ππ’π‘ πΆπΏ)=85.56MHz
- Gain = 28, CL = 20f
- Various calculations for PMOS and NMOS.
- Gain = 28, "CL" =20f
- For PMOS:
- Taking πΊπ= 8 * 0.43mS = 3.44 mS
- As, Av=Gm*Rout Rout = Av/Gm=8.139K
- Vb(PMOS) = 1.0296 V Vsg=0.7704
- From ADT, For Vsg =0.7704 Gm/Id is Calculated πΊπ/πΌπ=5.658 Id=607.8U
- Now, for the above Gm/Id πΊπ/πΊππ =47.92, πΌπ/π=10.51
- Hence , Gds = 71.7uS W = 57.84u
- For NMOS:
- As, Rout = Ro(NMOS) || Ro(PMOS) Gds(NMOS)= 1/π πππ - Gds(PMOS)
- Hence , GDS(NMOS)= 48.5uS
- Now, as the current will remain the same i.e 607.98uA
- πΌπ/(πΊππ (ππππ))=12.534 using this From LUT in ADT, Gm/Id is calculated for NMOS
- Hence, πΊπ/πΌπ=5.61 Gm (PMOS) = 5.61 * 607.98uA = 3.41mS
- For, πΊπ/πΌπ=5.61, πΌπ/π=36.7, Vgs=0.7913
- Hence, W= 16.56u
First Stage Schematic
Second Stage Schematic
Two-Stage Operational Amplifier Schematic
Transfer Function
Transient Analysis
Frequency Response
- "The Gm/Id Design Methodology Demystified" by Dr. Hesham Omran
- "CMOS Analog IC Design Lectures" by Dr. GS Javed
- "The Design of TWO STAGE Miller OpAmp: Final Verdict" by Dr. Hesham Omran
- NPTEL IIT Madras Course on OpAmp (Lecture 1, Lecture 2, Lecture 3)