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ahsan-ali-interests

My interests and some collaborations

alu-using-only-one-adder

In this repository, an ALU (Arithmetic and logic unit) is made using one full adder which can add as well as subtract using that adder only

biriscv

32-bit Superscalar RISC-V CPU

block-chain-network

This repository provides basic tools and instructions to setup a network of IBFT nodes

cocotb-examples

Some RTL files have been tested using cocotb (Python)

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

deeplearningexamples

State-of-the-Art Deep Learning scripts organized by models - easy to train and deploy with reproducible accuracy and performance on enterprise-grade infrastructure.

duty-cycle-and-frequency-controlled-signal-using-verilog

We will make a signal in Verilog which will be a variable duty cycle as well as variable frequency signal which is named as pulse. We can refer this signal pulse as a square wave also with variable duty cycle.

electronics-data

This repository contains some temporary data for some of my electronics projects.

github-actions

gnu-tool-chain-for-riscv-lite

We will use this tool chain to convert our C language codes to machine codes and assembly codes to machine codes for our own made RISC-V processor (Both single cycle and Pipelined).)

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

hangman-game-in-python

home

Repository for the github site

line-following-robot-with-pid-controller-in-tiva-tm4c123gh6pm

Line following Robot with C code

migen

A Python toolbox for building complex digital hardware

pak-dsp

Application class Digital Signal Processor that can be used in Signal Conditioning and Image Processing applications.

pak-dsp-caravel

pak-rv-core

RISC-V based Linux Capable Processor

risc-v-32i-5-stage-pipeline-processor

5 stage pipeline implementation of RISC-V 32I Processor.

riscof_compliance

This repository contains necassary configurations for running Architecture Compatibilit Tests on RISC-V based processors.

riscv-3-stage-pipelined-processor-core

Fully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also supported as they can configure and manage all the interrupt/exceptions.

riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

riscv-linux-boot

Trivial RISC-V Linux binary bootloader

school-management-system-in-python

In this Project, we will build a GUI-based School Management System using the Tkinter, SQLite3, and TkCalender libraries and messagebox and Ttk modules of the Tkinter library. It is an intermediate level project, where you will learn how to use databases and make some great GUIs in Python and apply them in real life. Let’s start!

simple-ready-valid-handshake-protocol-interface

In this repository, a simple ready-valid protocol is implemented in System Verilog and tested carefully according to AMBA specifications.

single-cycle-risc-v-implementation-in-system-verilog-with-verification

Fully implemented single cycle RISC-V with support of R, I, J, S, B and U type instructions. Also, formal verification test benches are written.

single-cycle-riscv-with-assembler

It is a repository on which single cycle RISC-V processor is made supporting R, I, S, B and J type instructions

speaker-identification-using-machine-learning

spi-protocol

SPI protocol is implemented and simulated successfully in this repository.