ahsanaliuet/riscv-3-stage-pipelined-processor-core

Fully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also supported as they can configure and manage all the interrupt/exceptions.

• 👋 Hi, I’m Ahsan Ali.
• 👀 I’m interested in Digital Systems, Embedded Systems Design, Operating Systems, Computer Architecture and IoT.
• 🌱 I’m currently learning BS Electrical Engineering specifically Embedded Systems and Computer Architecture
• 💞️ I’m looking to collaborate on my Final Year Project (FYP) and Embedded Systems Design and Chip Design
• 📫 I can be reached using my email ID. i.e., [email protected] and can also be reached using my WhatsApp number. i.e., [phone]