###MIPS Processor
This single cycle MIPS processor is the final project of EECE2322 - Digital Logic Design at Northeastern University. We developed this processor from the ground up, combining an ALU, register file, and data and instruction memory to form a complete MIPS datapath.
This processor is written in verilog, is completely synthesizable, and will include a complete testbench for simulation purposes. We also include a makefile for building and testing using iverilog.
##Authors Alex Interrante-Grant James Massucco
This project is open source under the MIT Public License.