alanjian85/trinity

A rasterization-based GPU created for real-time rendering

Project Trinity

A rasterization-based GPU created for real-time rendering

Overview

The project Trinity, as its name implies, is not only an open-source hardware implementation of a graphics processing unit (GPU). In essence, It consists of a GPU hardware together with its driver and architecture (and tools targeting the architecture). They are all a piece of Trinity.

The motivation is to build a full-featured and open-source GPU that can runs on common FPGA platforms. Presently, It is primarily written in Scala and Chisel, an open-source and relatively high-level (in comparison with Verilog, SystemVerilog and VHDL) hardware description language (HDL) that can be used to describe combinational and synchronous circuits.

On the contrary with other open-source GPUs, the ambition of this project is to build a hardware that supports both 3D real-time rendering and programmable pipeline (in the form of shader, a program that models the shading of objects with its parallel nature) at the same time. And the ultimate goal is to support modern graphics APIs such as OpenGL 4 and Vulkan.

Features

• Support for any screen resolutions with width no greater than 1024
• Support for any RGB format whose channel width is a power of two greater or an arbitrary integer less than 4

Build instructions

Vivado

Before building this project, the EDA tool AMD Xilinx Vivado must be installed and the required platform files must be downloaded and put to the appropriate place (See Installing Vivado, Vitis, and Digilent Board Files). Additionally, instructions in the Chisel setup manual should be followed to have the correct environment for Chisel.

If all dependencies are installed and set up properly, the first step is to clone the GitHub repository and compile the Chisel code in the project directory:

git clone https://github.com/alanjian85/trinity && cd trinity
sbt run

There should now be some SystemVerilog files in the generated directory. And the second step is to run Vivado in the vivado directory and execute the TCL script build.tcl. If you click the Generate Bitstream button now, you will get a file that can be loaded into FPGA. Then you can see the result on the screen connected to your FPGA board.

Verilator

Trinity also offers simulation option through the use of Verilator, a program that converts Verilog source code to C++ code. A C++ test bench displaying the output of Trinity using SDL2 is also included and can be used in conjunction with the code generated by Verilator.

git clone https://github.com/alanjian85/trinity && cd trinity
sbt "run --verilator"
cd verilator
make

An executable file trinity will then be generated in the obj_dir directory. Run it and you will see a window shows up and displays the execution result of this GPU.

References

• Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions (UG586)
• 7 Series FPGAs AXI Multi-Port Memory Controller Using the Vivado IP Integrator Tool (XAPP1164)

License (MIT)

MIT License

Copyright (c) 2023 Alan Jian

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions: