alcatrazescapee/elec-374

ELEC 374 CPU Design Project

elec-374's Issues

Task: Registers + Bus

Need to implement the following registers (which are all the same general register)

• R0 to R15, PC, IR, Y, Z, MAR, HI, and LO (although snake_case name them ofc)
• Possibly add a module for the register file itself?

Bus:

• Implement a single bus (this seems awful and inefficient but whatever, it's what is suggested to start with and do a 3-bus architecture later for bonus marks)
• Suggestion would be to use 32-1 mux + encoder style, as tri-state is gross and I don't want to have to deal with it.
• Connect all the registers to the bus. (in the cpu top level module?)

Task: Simulation / Report

This is all the simulation / verification requirements the project / phase 1 description states. I would assume we have more (also automated ones, because those are cool), but we need to complete at least:

• (3a) Simulate and R5, R2, R4
• (3b) Simulate or R5, R2, R4
• (3c) Simulate add R5, R2, R4
• (3d) Simulate sub R5, R2, R4
• (3e) Simulate mul R2, R4
• (3f) Simulate div R2, R4
• (3g) Simulate shr R5, R2, R4
• (3h) Simulate shl R5, R2, R4
• (3i) Simulate ror R5, R2, R4
• (3j) Simulate rol R5, R2, R4
• (3k) Simulate neg R5, R2
• (3l) Simulate not R5, R2

And final report:

The phase 1 report in hard/soft copy (one per group) should include:

• Printouts of your HDL codes, and schematic (if any)
• Printout of your testbenches (if they are similar, just include one and discuss the differences for
  the other cases).
• Functional simulation runs for all the tests
• Reports should be submitted online through OnQ for the first half of the term.

Phase 3: Interrupts / Exceptions

The following signals already exist:

• ALU Divide by Zero

elec-374/project/hdl/cpu.v

Line 190 in 1036ad5

.divide_by_zero(), // todo: exception handling

• Floating Point Cast out of Bounds

elec-374/project/hdl/cpu.v

Line 202 in 1036ad5

.cast_out_of_bounds(), // todo: exception handling

• Floating Point Cast Undefined

elec-374/project/hdl/cpu.v

Line 203 in 1036ad5

.cast_undefined(),

More could be added - undefined add/multiply/divide, undefined operation during reciprocal, possibly others?

Task: MDR Unit

Fairly straightforward, Mux + Register, as per on the spec

• Implement MDR
• Connect it to the cpu / bus.

Task: ALU Operations

Need to implement the following instructions:

• add, sub
  • Required: an adder subtractor. RCA, SCA, or CLA ?
  • n-bit RCA
  • 32-bit CLA or other composition of adders for greater efficiency aka bonus marks?
• mul
  • Required: 32x32 Booth multiplier, with bit-pair recoding.
  • CSA reducer tree / Wallace Tree (no carry chains from RCAs in the sum, and a CLA at the end?)
• div
  • Likely want to write our own generic adder/subtractor, for both div and mul (maybe a CSA as well?)
  • Array divider of some form?
• and, or, not: None of these need a module of their own, they are one-liners.
• neg (Negate)
  • Signed Compliment module.
• shr
  • This is a logical shift (Java >>> operator).
• shl
• ror
• rol
• ALU itself needs a module

Optional: Test Improvements

Issues:

• Tests can have weird dependency resolution issues, i.e. a test that fails to compile will still attempt to simulate.
• Tests have ordering issues when run in isolation, i.e. running the datapath test will not recompile the ALU if changes were made.
• Verilog (the version we are using) does not support the type of floating point values we would need to be able to do proper floating point tests.

Solution: Makefile! (and some other buisness)

Phase 3: Report, Simulation

• Need to simulate the demo program.
  • Waiting on control unit completion.
  • Assembly program has been transpiled + compiles.
• Report writing (will be much shorter this time).
• Possibly need to look into a .mif for proper initialization.

Phase 2 Components

• 2.1 Memory Subsystem
  • Synchronous or Async memory block (512 words)
  • Connect to datapath
• 2.2 Select and Encode Logic
  • Connect IR fields to RF address fields.
  • Sign extend the constant C and connect to ALU input.
• 2.3 Revision to R0
  • We implemented R0 as a no-op register, thus this step functions the same
  • In compliance with the spec, this needs to be done properly.
• 2.4 CON FF Logic
  • Use the ALU subtraction out, and IR C2 field to detect =, !=, < and > flags
• 2.5 Input / Output Ports
  • Design IO registers that are interfaced through the in / out instructions, and connect to datapath.
  • Strobe / asynchronous signal for when data is ready.

Phase 3: Control Unit Implementation

Already Done:

• All ALU + FPU Instructions, mfhi, mflo, Memory instructions, ALU Immediate instructions.

Still To-Do:

• Branches (brzr, brnz, brpl, brmi`)
• jal
• jr
• in / out - Anything we need to do control wise w/ enable / wait signals for async IO?
• nop
• halt - It exists but it does not do anything. Both halt, reset signals need to be implemented in hardware

Phase 2 Simulation

Simulations of the following instructions (might need to modify the ones that potentially write to r0:

• ld r1, 85
• ld r0, 35(r1)
• ldi r1, 85
• ldi r0, 35(r1)
• st 90, r1
• st 90(r1), r1
• addi r2, r1, -5
• andi r2, r1, 26
• ori r2, r1, 26
• brzr r2, 35
• brnx r2, 35
• brpl r2, 35
• brmi r2, 35
• jr r1
• jal r1
• mfhi r2
• mflo r2
• out r1
• in r1