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A verifier for Factorio blueprints, enabling one to automatically check logical properties

License: GNU General Public License v3.0

Rust 99.12% Nix 0.88%
factorio rust verifier sat

verifactory's Introduction

VeriFactory

VeriFactory is a verifier for Factorio blueprints, enabling you to automatically check logical properties on a blueprint. Currently this is limited to checking whether or not a belt-balancer works and if the inputs get all drained the same, leading to no imbalances.

How it works

  • A blueprint is loaded via File > Open blueprint, File > Open blueprint file or by pasting with the Ctrl+V shortcut.
  • Automatically added inputs/outputs should be removed accordingly (Every belt or splitter ending or starting from nothing gets flagged as input/output).
  • Every entity of the blueprint is then transformed into one or more nodes in a graph (using an intermediate representation).
  • The graph is simplified and the throughputs of the different edges are minimized as much as possible.
  • Using a SAT solver, like z3, the graph is turned into a series of logical formulas and constraints.
  • These constraints can then be used to prove or disprove certain logical properties.

Performance

Although no optimizations have been made the verifier is extremely performant. This is due to the fact that the verifier does not need to try all the combinations of inputs and simulate the actual blueprint, relying instead on the resolution of logical formulas using a SAT solver.

Take for example the following 64x64 belt balancer. To load and verify both belt-balancing and equal-drain properties it takes less then 1 second! With any other tool this would take considerably longer.

Features and Todos

  • Standard properties:
    • Belt balancing
    • Equal input drain
    • Throughput unlimited
    • Universal balancer
  • Counter example generation
  • Correct colors for the different belts
  • Find a nice way to visualize or export a counter example
  • Resizable and movable canvas
  • Support for dual-lane belts
  • Resizable and movable canvas
  • Support for inserters and assemblers
  • Custom language to express arbitrary properties
  • DOCS!

Installation

The latest version of the program can be found here for both Windows and Linux. This option ships VeriFactory bundled with z3.

Building from source

VeriFactory can be compiled either with z3 bundled with it or needing a valid installation of it on the system. For Windows it is recommended to go for the bundled version.

Building the standalone version

To build: cargo build --release. To run: cargo run --release. Executable can be found in target/release.

Building the bundled version

To build: cargo build --release --features build_z3. To run: cargo run --release --features --build_z3. Executable can be found in target/release.

Contributing

Warning! The project is still in a very early stage, thus lots of design choices are still open and the code quality is very low

Pull requests are welcome. For major changes, please open an issue first to discuss what you would like to change. Note that documentation is non-existant and the design document is mostly incomplete. Bug reports are greatly appreciated. :)

Design Document

More information about how the project is structured can be found under this link. This includes the design document specifying how the underlying conversion from Factorio blueprints to the z3 model works.

verifactory's People

Contributors

alegnani avatar axelmontini avatar

Stargazers

 avatar R_O_C_K_E_T avatar Samir Rashid avatar  avatar Pavlo Tokariev avatar Ignas Kiela avatar  avatar Trenten N avatar Emily Delorme avatar Nayumii avatar Loïc Gremaud avatar mojamuto avatar  avatar Ean Milligan avatar  avatar Arthur Meyre avatar  avatar Patrick Frampton avatar Davi avatar Amos Herz avatar

Watchers

 avatar Ignas Kiela avatar  avatar

Forkers

guyslain

verifactory's Issues

Aggressive shrinking loses side information on edges

When applying aggressive shrinking to a graph the side information on the edges leading out/in splitters gets lost. This causes splitters with either Left or Right priority to explode due to an unwrap of a None.

Incorrectly marks non-TU balancer as TU and non-TU as universal

First Blueprint:

0eNqlV8GOmzAQ/RXLp1aCCBsSIMdKu1Klqqe2l7ZakeAEq8Yg2ySNovx7DaxSkmUTD7klxvMeb8bzGB/xSjSsVlwavDzinOm14rXhlcRL/OmAnjNtMpk/c13wqtEz9EuGPkXfvqNVJjK5ZgrxDeKyboxGmWJo0wiBKoVYWZuDh1aNQaZQVbMt7BZf8JIblrcxpmBI85wNg4tMbPwOwXJ2O0qe5+J1D+K6h/+gWC2yNWt3lGjPTYEOTIhqj1ZMWChTIc3Yxxn2MF9XUuPlzyPWfCsz0Yo0h5pZdTuuTGNXPCyzsl3od/hP+GTjZM7+4iU5eYDIH4NICor8PIgMQZFfBpHR6beHmTTccNaL7v4cXmRTrpiycs7RRmVS15Uyfpsyi1pXmvdlP2IL5ZMFDWdzDx/a30ESzeaWJ+eKrftdnb4reAqCp7fgoxH48Ay/safSd+GIBhzURUJ0yaFrwY2xD+4qoFfYHq4aYw/ti+2tSlkKCynYxuAR0vmZtLGFVFvbLjJ3LEzYqXo9JD3lGMUCnrsQmrt4cvlDF/gEUppgiH4fOwW9OoFmhgST8Z1SQwi4vCQFi6CAApDkZm90fu7SGuTBpg+clEWPkRAnkvlUawkcrEXxbTGewKvOhzvMW3Vnv+nKOMoaP+Y3bmUDOcKwqYgDeDolb4Fb3t73aRrAExfcStzYh5SC5oCLVnYqDAU5RQorDA0h4AsgONwJSAx1Agpxggv4wAEc/qUnc7CC+DESt1OUTB+L4nQ4Fr1rUzSdOrLEybWExdjEGkwduDv8MUQydZJ4Tcm9GZtOxnfLSPiQv70VMXZywuihcciRZA4nSW6T2NubvR2XFvH/pdzDIrOAdu1pxwVqL99fmdlX6o99tGNK97EJieKUxglN4yBJT6d/mF8apw==

Test results:
Belt-balancer: Yes
Input-balanced (if belt-balancer): No
TU (if belt-balancer): Yes
Universal: Yes

This blueprint is not TU however; if the two outer input belts receive only 15 item/s and the inner receives the full 30 item/s, the output is still limited to a total of 45 item/s. See https://imgur.com/a/DVMmcIK for a visual.
I think this might be because the balancer uses mixed belts: most are red/fast, but some are yellow/normal.

Second blueprint:

0eNqlWk1v4zYQ/SuETi1gB/wQRTLHAlmgQNtTt5e2WMg2E7OVJUGikjUC//fS9mJXcaTujOYSJA45j/PImXkc8zXbVINvu1DH7P412/l+24U2hqbO7rOfjuxD2cey3n0I/T40Q/9XrdaS/f6RbcqqrLe+Y+GRhbodYs/KzrPHoapY0zF/aONxxTZDZHHfNcPTPg1ZV+EQot+d58S9Z+Xun3Lr6zg2sC+rx/XFSkK9jGrSj+46hIX+ivBD59sqzT0POLCXEPfs6KuqeWEbXyVLsWG99z/eZassbJu6z+7/fM368FSX1dnLeGx9cu85dHFIn6yyujycP7iOWD9kpzSv3vnP2b04rRAz/xjNlKiZP49mKtTMX0Yz89PfqywxGmLwV6cvfxw/1cNh47vkztfZj2lj17Er675turg+85ZMt00frpv/miV7a1EocadX2fH8u+D8TiewXej89jrq4uQNhnyL0bdViDH9Y9I6H1v/vm2FX/8YQdyuv5jAyGkcvcPIJzA0giNpcRwV6PVLh+XI4DEsFsPiMczNWZ2w6mhWQSsXHA+isWEm8LEs8/8DmTqnQuKDofgKwp0FebIgqg0aZEFYazSIxoPkaBB8gCuFBsFHuJJoEEtJ51AQh6lHYmTeAWodpyRboAdSULItFETSPHEgEHykS3Q6kTklxUNBNA0ERldBowsGYijFCkqXpRQrKIijeeKmFYO6ifEhae3uKV1q6h1w9e/2IZ3QL6r+cq/JplAXBP1tlp8yi1Hn8k1GB6hzRVsz6LyqBeEt0SAogc6RNBUY48iKpAym3I2PfwEwbjHGxyFgAMZRhVrhVp5zmmgykFOTC5pogoFIyv00kQUCUQty3htt9h7m+zkvz2muGciVJl9494Yds4KmomCbY2ggMJosTXQaUKsFE/JvpA1gLzSnqSeQB1rQdCAMRNKETTGtBbSiibI5szlttTBKNG3toFSriyXKT8GyYDPEmTSozVKNBokKS9NoMOIWKHGOTYPFgvgWWE8KfHwLi/YEI8qFw8mqQtE8gNGU01p4OQhE00A0CKSgdTxhnhgaCMwTu/QmkAOMO1qnE0ST4TQQEE1GLL12AGgyknYjgNGkaCAwmojaHOaJpjWEYSAFzRMYXYbmCQzELr3KQI6uo90yQHthif1zEE1WLL1lAGiyknYBgNGkaCAwmnIMTeN6ATFO1Ot6+q5hC5qazWfMGlqPEbapRCUO21S3tNcIMO44TebPbKoTS7uMCrBmSWsESgjrjliRYSDEiixn2Nc0swq09oLaX1QL+ouO2DibY4zYKpOQhocjlmPQtgjOaYVGwp7HCFpnDohC7JoBURT120E5/+3gfI9IcGKXTYGe/3BN9U4t6YAJXtAK8EykCk4s7GrOLrGWz9p1NNkkYC/JOG31QBRB4/6Mcn7fGqI/JBvf3i2vsqpMJtJnD8++Zr82nWcPz6Fi57fKv/n40nT/pkHPvuuvq7MiN04aK53h1p1O/wG71Gqk

gets results:
Belt-balancer: Yes
Input-balanced (if belt-balancer): No
TU (if belt-balancer): No
Universal: Yes

whereas it has a throughput oscillating between 45 and 60 item/s if the inputs that are next to each other receive 15 item/s each, and the other input receives 30 item/s, so is definitely not universal/UTU. Does the universal proof assume the balancer is TU?

UI feature requests

There is no scrolling in the GUI, and parts of it get hidden if the blueprint is too large (at least on Windows). (You probably already knew this.)

It would also be nice if there were a hotkey for (de)selecting entites as input/output.

Hangs whilst proving

Hi!
It would probably be a nice (and quite simple to implement) to run the proof on a seperate thread (maybe even in parallel for the different proofs!) so that the UI does not hang.
I would love to implement this if you agree it would be useful!

Long execution time of throughput unlimited proof

BP:

0eNqlmttO4zAQht/F1+nKZzt9Du5WqGohQpFKGuWAQKjvvi6n3S3jZPxzVdGSr38mM789476Kw3Fu+qHtJrF9Fe3dqRvF9verGNuHbn+8vDe99I3Yiqd2mOb0TiW6/ePljff/2ERxrkTb3TfPYqvOFXilLrry5p8rzfm2Ek03tVPbvEt/++Nl182Ph2ZIor6ubp77oRnHzTTsu7E/DdPm0BynRO9PY7r81F2+OiE3phIv6aU+X1Rd4XQ5zi7gTDlOLeBsOU4v4FwxbkmcL6bJBVoopi091lhMW4pb/Y02p2wdHoZTel1Jk5By+yP/T/PUz5MgvkDJb98w9sd2mtKHxCP+5T7ZFEuVsMwnK5Isjdy5KrlzU6JWLau1gFpZItYViFXLT8kXoOTybcOlQyuLBcr0srIaNmtPmrWE3dqn53vfDs3d+2eaoiuY7ki1Gr57x1BbVDhfGUQrRQrnc6W51vpVR22XKSPt4GWNTgsPr7pXaeEpegCCo1Zik/cYHdFllZPiNboDIANvJOo8NE6hODKrjUY3ATTOoDj6Zi20TFuS5ZD6/Yid4ax8xsPeaEjFAS5ZOgIRthS7Xjam/oE/suJrJVr15n/5loIrtOrNuj1ajcItA27QsJBZYi1qMDTOoTiyJqxHDYYTSWQVK8rgCDuEJqOB7x31ejichP2CQ1ewu3HoGtau1r3O4SMMDt3imynNSUPnUMfgRN6jXscJTUCVc+ARtSqyOF2N4hQ5SSoZf3ykcupo1m/bK3xyI8/rnYyHx4d0HAy+j7tKAs+oFQ+PFyWpHm7r6GB4fPbEenYBaaBpqRH0BclIYbRlI5UGCY/IODENaAen1s03aJAt13fIwcC7o2zd5YNk8SrXxcOW4FCL0uvJGeC2kNwBh4A6CI2LyGyZXPBCjZsRa/scJTAPJqVGBZc4Tyna8JHPKBqwqhmtaUTbPb3uGNHBjqHLh4LRF2+QzPX+iIxQQOuXbIgj3AOSE7dY40bpGKtVLdFWh9Fw1wr1MjK09Q9O4lixMPiIi8W3YHfDCTV6rs1he7hhZYUlwGbNwqNtH1mPNdr1MeKspIQNlRMJJeHTPXJ8r6RGjuwzLIOcBdCnt9IibU1Gl0M2UBldHjg7z8gKwF4powotkIyyGjg7z/yKQ6LzT/ooXsH5n+FpdPHM8Ay6XmZ4FlwUMjh0rpjBeTDvMrgAHh0k3G0l2ql5TJf+/e1gJY77dFl6L+7ibpp3h/1x3929ZfFTM4xvmGCkisHXVibKHzoArTo=

Reference this reddit post.

Can't find counter-example of broken belt balancer

We model a 4-4 belt balancer that is broken by setting the output priority of the middle splitter to Left. With an input of | 1 | 0 | 0 | 0 | we should be able to find that this does not respect the predicate of belt balancers.
The predicate (pred) for belt balancers is that all outputs are equal.
Thus we should be able to find a counterexample by checking cost = 0 and !pred.
We get that this is Unsat.

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