antmicro/fastvdma

Antmicro's fast, vendor-neutral DMA IP in Chisel

Fast Versatile DMA

Copyright (c) 2019-2023 Antmicro

Overview

FastVDMA is a DMA controller designed with portability and customizability in mind.

Supported features

• Interrupts
• 2D transfers with configurable stride
• External frame synchronization inputs

Supported buses

• Data
  • AXI4
  • AXI-Stream
  • Wishbone
• Control
  • AXI4-Lite
  • Wishbone

Dependencies

Because the controller is written in Chisel, it requires sbt, scala and java to be installed; additionally the tests require imagemagick.

Simulation

FastVDMA can be simulated as a whole but certain components can be tested separately.

You can simulate the full memory to memory design by running:

make testM2M

And the full stream to memory test by:

make testS2M

Each test run generates a .vcd file which can be opened using GTKWave or any other .vcd viewer. Output files are located in a separate sub directories inside the test_run_dir directory.

The full test should generate an outM2M.png/outS2M.png file demonstrating a 2D transfer with configurable stride. The resulting image should look similar to:

Synthesis

To generate a synthesizable verilog file either proceed with the default configuration by running:

make verilog

Or provide a valid configuration file with:

make CONFIG_FILE=<path_to_json_file> verilog

The generated file will be named DMATop$(configuration).v where configuration is chosen configuration of buses in the DMA. Verilog module will be named in the same manner. See the documentation on how to provide custom configuration -- link here.

Source code structure

• src/main/scala/DMAController contains sources of the DMA controller
  • Bus contains definitions of various bus bundles
  • CSR contains code responsible for handling configuration registers
  • Frontend contains modules handling various bus types
  • Worker contains generic code supporting controlling the DMA behavior
• src/test/scala/DMAController contains tests
  • Bfm contains Bus models that are used in full configuration tests
  • Frontend contains tests used for generating timing diagrams for various bus types
  • Worker contains tests that generate timing diagrams for the generic part of the DMA

fastvdma's Issues

Any example design in Vivado?

Is there any example/reference design uploaded somewhere for Vivado or any other platforms?
I am having issues with memory mapped addressing in Vivado and I wanted to figure out if I am building things correctly.

Documentation for use as AXI4 Stream target

Hi,
Is there/can you provide documentation on how to use the DMA Controller as a target for an AXI4-Stream.
In this case, I am using the DMA controller in Renode. I am streaming data to the AXI4-Stream input interface of the VDMA. I want to direct this data to a memory peripheral on the system bus.
How can this be achieved?

I have seen the axi.robot example file where the VDMA is configured to do a block transfer.
Configuring the VDMA writer the same way as in this example does not transfer any data to the memory peripheral.
From looking at the waveforms of the VDMA the stream data is reaching the TDATA input of the VDMA and there is one data value present on the w_data port of the VDMA however, this value is not sent on the system bus nor are any other values present on the w_data port on the writer.

Can you please advise?
Regards

CSR Memory map

Hey, could you provide some description(memory map) for the CSR?
In tests we can see some cryptic numbers:
DMAFull.scala

  axil_master.writePush(0x10, 0)
  axil_master.writePush(0x14, width)
  axil_master.writePush(0x18, height)
  axil_master.writePush(0x1c, 0)

  axil_master.writePush(0x20, height * width * 4 + width * 2)
  axil_master.writePush(0x24, width)
  axil_master.writePush(0x28, height)
  axil_master.writePush(0x2c, width)

Trying to change read interface to AXI4, getting elaboration errors when generating verilog

Steps to recreate:

1. Have dependencies installed (sbt, jdk, scala), clone fastvdma repo, and navigate to the cloned repo directory.

2. Make the following edits:

File: src/main/scala/DMAController/DMATop.scala
Line 36:

-    val read = Flipped(new AXIStream(DMATop.readDataWidth))
+    val read = Flipped(new AXI4(DMATop.addrWidth, DMATop.readDataWidth))

Line 44

-  val readerFrontend = Module(new AXIStreamSlave(DMATop.addrWidth, DMATop.readDataWidth))
+  val readerFrontend = Module(new AXI4Reader(DMATop.addrWidth, DMATop.readDataWidth))

3. Run "make verilog"

I get the following elaboration error:
[error] (run-main-0) chisel3.internal.ChiselException: Connection between left (DMAController.Bus.AXI4@203) and source (DMAController.Bus.AXI4@42b) failed @.r.rready: Both Left and Right are drivers

Is there something I'm missing? Perhaps some documentation is needed to guide through the steps to modify the bus protocol for each of the three interfaces (Ctrl, ReadData & WriteData)? Let me know what you think.

Getting error wile running "make test/testall" in master branch

Cloned master branch and installed dependencies (sbt, scala, java & imagemagik) as described in Readme. After that while running "make test/testall" got error as shown in below snapshot:

Nit: plural of bus is buses

Seee https://www.grammarly.com/blog/busses-buses/

Documentation for the CSR fields?

Hi,

I'm looking for any documentation about the fields of the CSRs in the design. I'm trying to write software to handle the DMA controller in a design with a RISC-V core, and I'm having trouble with understanding which bits of the registers to program. Is there anywhere I can find documentation on what the fields of each register are, and a brief description of their operation?

Thanks

To enable MM2S channel, need to know configurations

Cloned linux-readme branch and ran make verilog to generated verilog files. Able to see verilog file but by default only S2MM channel is enabled, tried configuring DMATop.scala to enable MM2S but some unknown error shown in below snapshot. Need to know how to enable MM2S channel. Below are the steps I followed:
--> git clone https://github.com/antmicro/fastvdma.git -b linux-readme
--> cd fastvdma
--> make testall (able to generate out.png)
--> make verilog

Is fastvdma tested on rocketchip?

FastVDMA was verified in the xc7z030fbg676-2 chip

hi, is Fastcdma tested on rocketchip?

will fastvdma support tilelink directly？

Could use a better name

FastDMA covers a lot of space.

Something like chisel-fastgraphicsdma ?