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Risc-V pipelined CPU and SoC written in SystemVerilog

Verilog 26.66% Fortran 0.01% Tcl 0.87% Shell 0.73% SystemVerilog 4.50% Mathematica 0.01% VHDL 49.57% Stata 0.01% C 10.99% C++ 4.39% Makefile 0.03% Assembly 0.01% CMake 0.01% HTML 1.88% CSS 0.01% Roff 0.33% M4 0.02% XSLT 0.01%

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