apritzel/u-boot

various u-boot patches

u-boot's Issues

status of the eachlink-h6-mini-WIP branch?

hi @apritzel - what is the latest state of the eachlink-h6-mini-WIP branch of this tree - how far did you get with the libdram case and with your own timinigs taken from the eachlink box? i'm asking, because i'm currently trying to get this working too on a qplus h6 tv box and got to the point that i have uboot running properly with libdram, but looks like booting a linux kernel hangs and without libdram it hangs early on with "DRAM:". the details of my tries can be found here: https://forum.armbian.com/topic/10174-since-tanix-tx6-can-boot-from-the-sd-card/# - any advice, hint or latest status from you would be very helpful.

a lot of thanks in advance and best wishes - hexdump

erro recompile u-boot-with-spl.bin h616

I'm trying to compile - u-boot-with-spl.bin with the dtb that I extracted from the device, but when trying to do this it takes as a base other dtbs marked with an asterisk and the error below appears, I've already tried to modify everything way but the error always appears:

CC net/net.o
CC net/ping.o
CC net/tftp.o
AR net/built-in.o
LDS u-boot.lds
LD u-boot
OBJCOPY u-boot.srec
OBJCOPY u-boot-nodtb.bin
RELOC u-boot-nodtb.bin

• DTC arch/arm/dts/sun50i-h616-orangepi-zero2.dtb *
• DTC arch/arm/dts/sun50i-h616-x96-mate.dtb *
  DTC arch/arm/dts/box-novembro.dtb
  arch/arm/dts/box-novembro.dtb: ERROR (path_references): /aliases: Reference to non-existent node or label "mmc0"

Question: SPL defconfig?

Hello,

$ export CROSS_COMPILE=arm-linux-gnueabihf- $ make sun50i_spl32_defconfig $ make

Do you know which repo/branch contains the SPL defconfig? It does not appear to have landed yet in the denx repo (or more likely I have not been abel to find it).

Any suggestions? Many thanks.

about h616/h313 emmc boot

I designed an h313 board，I can use the sd card boot uboot and linux ，in linux i tested emmc driver it is ok 。it can work steadily for hs200，but when i use emmc boot，spl boot but uart print :
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices

ERROR ### Please RESET the board

and debug info:

U-Boot SPL 2021.01-rc5-armbian (Apr 26 2021 - 04:47:20 -0700)
DRAM:testing 32-bit width, rank = 2
read calibration failed!
testing 32-bit width, rank = 1
read calibration failed!
testing 16-bit width, rank = 2
read calibration failed!
testing 16-bit width, rank = 1//wo use 16bit ddr3
MBUS port 0 cfg0 0100000d cfg1 00640080
MBUS port 1 cfg0 06000009 cfg1 01000578
MBUS port 2 cfg0 0200000d cfg1 00600100
MBUS port 3 cfg0 01000009 cfg1 00500064
MBUS port 4 cfg0 20000209 cfg1 1388157c
MBUS port 5 cfg0 00640209 cfg1 00200040
MBUS port 6 cfg0 00640209 cfg1 00200040
MBUS port 8 cfg0 01000009 cfg1 00400080
MBUS port 11 cfg0 01000009 cfg1 00640080
MBUS port 14 cfg0 04000009 cfg1 00400100
MBUS port 16 cfg0 2000060d cfg1 09600af0
MBUS port 21 cfg0 0800060d cfg1 02000300
MBUS port 25 cfg0 0064000d cfg1 00200040
MBUS port 26 cfg0 20000209 cfg1 1388157c
MBUS port 37 cfg0 01000009 cfg1 00400080
MBUS port 38 cfg0 00640209 cfg1 00200040
MBUS port 39 cfg0 20000209 cfg1 1388157c
MBUS port 40 cfg0 00640209 cfg1 00200040
512 MiB
SPL malloc() before relocation used 0x0 bytes (0 KB)

SPL: board_init_r()
Trying to boot from MMC2
init mmc 0 resource
init mmc 0 clock and io
mmc 0 set mod-clk req 24000000 parent 24000000 n 1 m 1 rate 24000000
size=x, ptr=1a0, limit=1a0: 4fd00000
init mmc 2 resource
init mmc 2 clock and io
mmc 2 set mod-clk req 24000000 parent 24000000 n 1 m 1 rate 24000000
size=x, ptr=1a0, limit=340: 4fd001a0
clock is disabled (0Hz)
set ios: bus_width: 0, clock: 0
set ios: bus_width: 1, clock: 0
clock is enabled (400000Hz)
set ios: bus_width: 1, clock: 400000
mmc 2 set mod-clk req 400000 parent 24000000 n 4 m 15 rate 400000
CMD_SEND:0
ARG 0x00000000
mmc 2, cmd 0(0x80008000), arg 0x00000000
mmc resp 0x00000000
MMC_RSP_NONE
CMD_SEND:8
ARG 0x000001aa
mmc 2, cmd 8(0x80000148), arg 0x000001aa
cmd timeout 100
RET -110
CMD_SEND:55
ARG 0x00000000
mmc 2, cmd 55(0x80000177), arg 0x00000000
cmd timeout 100
RET -110
CMD_SEND:0
ARG 0x00000000
mmc 2, cmd 0(0x80008000), arg 0x00000000
mmc resp 0x00000000
MMC_RSP_NONE
CMD_SEND:1
ARG 0x00000000
mmc 2, cmd 1(0x80000041), arg 0x00000000
mmc resp 0x00ff8080
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:1
ARG 0x40300000
mmc 2, cmd 1(0x80000041), arg 0x40300000
mmc resp 0x00ff8080
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:1
ARG 0x40300000
mmc 2, cmd 1(0x80000041), arg 0x40300000
mmc resp 0x00ff8080
MMC_RSP_R3,4 0x00ff8080
CMD_SEND:1
ARG 0x40300000
mmc 2, cmd 1(0x80000041), arg 0x40300000
mmc resp 0xc0ff8080
MMC_RSP_R3,4 0xc0ff8080
CMD_SEND:2
ARG 0x00000000
mmc 2, cmd 2(0x800001c2), arg 0x00000000
mmc resp 0xa27646c1 0x3002a021 0x30344741 0x11010030
MMC_RSP_R2 0x11010030
0x30344741
0x3002a021
0xa27646c1

                                    DUMPING DATA
                                    000 - 11 01 00 30 
                                    004 - 30 34 47 41 
                                    008 - 30 02 a0 21 
                                    012 - a2 76 46 c1 

CMD_SEND:3
ARG 0x00010000
mmc 2, cmd 3(0x80000143), arg 0x00010000
mmc resp 0x00000500
MMC_RSP_R1,5,6,7 0x00000500
CMD_SEND:9
ARG 0x00010000
mmc 2, cmd 9(0x800001c9), arg 0x00010000
mmc resp 0x924000e3 0xffffffe7 0x0f5903ff 0xd05e0032
MMC_RSP_R2 0xd05e0032
0x0f5903ff
0xffffffe7
0x924000e3

                                    DUMPING DATA
                                    000 - d0 5e 00 32 
                                    004 - 0f 59 03 ff 
                                    008 - ff ff ff e7 
                                    012 - 92 40 00 e3 

CMD_SEND:7
ARG 0x00010000
mmc 2, cmd 7(0x80000147), arg 0x00010000
mmc resp 0x00000700
MMC_RSP_R1,5,6,7 0x00000700
CMD_SEND:8
ARG 0x00000000
mmc 2, cmd 8(0x80002348), arg 0x00000000
trans data 512 bytes
cacl timeout 78 msec
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
size=x, ptr=200, limit=540: 4fd00340
CMD_SEND:6
ARG 0x03af0100
mmc cmd 6 check rsp busy
mmc 2, cmd 6(0x80000146), arg 0x03af0100
mmc resp 0x00000800
MMC_RSP_R1b 0x00000800
CMD_SEND:13
ARG 0x00010000
mmc 2, cmd 13(0x8000014d), arg 0x00010000
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
CURR STATE:4
clock is enabled (25000000Hz)
set ios: bus_width: 1, clock: 25000000
mmc 2 set mod-clk req 25000000 parent 588000000 n 2 m 12 rate 24500000
CMD_SEND:6
ARG 0x03b70200
mmc cmd 6 check rsp busy
mmc 2, cmd 6(0x80000146), arg 0x03b70200
mmc resp 0x00000800
MMC_RSP_R1b 0x00000800
CMD_SEND:13
ARG 0x00010000
mmc 2, cmd 13(0x8000014d), arg 0x00010000
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
CURR STATE:4
set ios: bus_width: 8, clock: 25000000
mmc 2 set mod-clk req 25000000 parent 588000000 n 2 m 12 rate 24500000
CMD_SEND:6
ARG 0x03b90100
mmc cmd 6 check rsp busy
mmc 2, cmd 6(0x80000146), arg 0x03b90100
mmc resp 0x00000800
MMC_RSP_R1b 0x00000800
CMD_SEND:13
ARG 0x00010000
mmc 2, cmd 13(0x8000014d), arg 0x00010000
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
CURR STATE:4
CMD_SEND:8
ARG 0x00000000
mmc 2, cmd 8(0x80002348), arg 0x00000000
trans data 512 bytes
cacl timeout 78 msec
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
clock is enabled (52000000Hz)
set ios: bus_width: 8, clock: 52000000
mmc 2 set mod-clk req 52000000 parent 588000000 n 1 m 12 rate 49000000
CMD_SEND:8
ARG 0x00000000
mmc 2, cmd 8(0x80002348), arg 0x00000000
trans data 512 bytes
cacl timeout 78 msec
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
spl: mmc boot mode: raw
CMD_SEND:16
ARG 0x00000200
mmc 2, cmd 16(0x80000150), arg 0x00000200
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
CMD_SEND:17
ARG 0x00000070
mmc 2, cmd 17(0x80002351), arg 0x00000070
trans data 512 bytes
cacl timeout 78 msec
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
hdr read sector 70, count=1
Found FIT
CMD_SEND:16
ARG 0x00000200
mmc 2, cmd 16(0x80000150), arg 0x00000200
mmc resp 0x00000900
MMC_RSP_R1,5,6,7 0x00000900
CMD_SEND:18
ARG 0x00000070
mmc 2, cmd 18(0x80003352), arg 0x00000070
trans data 710144 bytes
cmd timeout 180
RET -110
fit read sector 70, sectors=1387, dst=49f52840, count=0, size=0xad5a8
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
SPL: failed to boot from all boot devices

ERROR ### Please RESET the board

h6 atf hangs at the axp805 probe on some h6 devices

hello,

i just built a fresh mainline u-boot (2020.01) and mainline atf (head as of today from the github mirror) and on a h6 tv box without an axp805 the resulting u-boot with that atf in it will hang:

U-Boot SPL 2020.01-dirty (Jan 15 2020 - 21:56:28 +0100)                                   
DRAM:MBUS port 0 cfg0 0100000d cfg1 00640080                                              
MBUS port 1 cfg0 06000009 cfg1 01000578                                                   
MBUS port 2 cfg0 0200000d cfg1 00600100                                                   
MBUS port 3 cfg0 01000009 cfg1 00500064                                                   
MBUS port 4 cfg0 20000209 cfg1 1388157c                                                   
MBUS port 5 cfg0 00640209 cfg1 00200040                                                   
MBUS port 6 cfg0 00640209 cfg1 00200040                                                   
MBUS port 8 cfg0 01000009 cfg1 00400080                                                   
MBUS port 11 cfg0 01000009 cfg1 00640080                                                  
MBUS port 14 cfg0 04000009 cfg1 00400100                                                  
MBUS port 16 cfg0 2000060d cfg1 09600af0                                                  
MBUS port 25 cfg0 0064000d cfg1 00200040                                                  
MBUS port 26 cfg0 20000209 cfg1 1388157c                                                  
MBUS port 37 cfg0 01000009 cfg1 00400080
MBUS port 38 cfg0 00640209 cfg1 00200040
MBUS port 39 cfg0 20000209 cfg1 1388157c
MBUS port 40 cfg0 00640209 cfg1 00200040
 2048 MiB
Trying to boot from MMC1
NOTICE:  BL31: v2.2(debug):v2.2-321-g743600b2
NOTICE:  BL31: Built : 21:53:49, Jan 15 2020
NOTICE:  BL31: Detected Allwinner H6 SoC (1728)
NOTICE:  BL31: Found U-Boot DTB at 0xc07ae70, model: Eachlink H6 Mini
INFO:    ARM GICv2 driver initialized
INFO:    PMIC: Probing AXP805 on I2C
IN

if i comment out the apx805 probing, it works perfectly fine:

diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index 443015ba..a1e4d692 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -55,16 +55,16 @@ int axp_write(uint8_t reg, uint8_t val)
 
 static int axp805_probe(void)
 {
-       int ret;
-
-       /* Switch the AXP805 to master/single-PMIC mode. */
-       ret = axp_write(0xff, 0x0);
-       if (ret)
-               return ret;
-
-       ret = axp_check_id();
-       if (ret)
-               return ret;
+//     int ret;
+//
+//     /* Switch the AXP805 to master/single-PMIC mode. */
+//     ret = axp_write(0xff, 0x0);
+//     if (ret)
+//             return ret;
+//
+//     ret = axp_check_id();
+//     if (ret)
+//             return ret;
 
        return 0;
 }

resulting working boot:

U-Boot SPL 2020.01-dirty (Jan 15 2020 - 22:04:24 +0100)
DRAM:MBUS port 0 cfg0 0100000d cfg1 00640080
MBUS port 1 cfg0 06000009 cfg1 01000578
MBUS port 2 cfg0 0200000d cfg1 00600100
MBUS port 3 cfg0 01000009 cfg1 00500064
MBUS port 4 cfg0 20000209 cfg1 1388157c
MBUS port 5 cfg0 00640209 cfg1 00200040
MBUS port 6 cfg0 00640209 cfg1 00200040
MBUS port 8 cfg0 01000009 cfg1 00400080
MBUS port 11 cfg0 01000009 cfg1 00640080
MBUS port 14 cfg0 04000009 cfg1 00400100
MBUS port 16 cfg0 2000060d cfg1 09600af0
MBUS port 25 cfg0 0064000d cfg1 00200040
MBUS port 26 cfg0 20000209 cfg1 1388157c
MBUS port 37 cfg0 01000009 cfg1 00400080
MBUS port 38 cfg0 00640209 cfg1 00200040
MBUS port 39 cfg0 20000209 cfg1 1388157c
MBUS port 40 cfg0 00640209 cfg1 00200040
 2048 MiB
Trying to boot from MMC1
NOTICE:  BL31: v2.2(debug):v2.2-321-g743600b2-dirty
NOTICE:  BL31: Built : 22:03:55, Jan 15 2020
NOTICE:  BL31: Detected Allwinner H6 SoC (1728)
NOTICE:  BL31: Found U-Boot DTB at 0xc07ae70, model: Eachlink H6 Mini
INFO:    ARM GICv2 driver initialized
INFO:    PMIC: Probing AXP805 on I2C                                                      
WARNING: PMIC: No PMIC DT node, skipping setup                                            
INFO:    BL31: Platform setup done                                                        
INFO:    BL31: Initializing runtime services                                              
INFO:    BL31: cortex_a53: CPU workaround for 855873 was applied                          
INFO:    BL31: Preparing for EL3 exit to normal world                                     
INFO:    Entry point address = 0x4a000000                                                 
INFO:    SPSR = 0x3c9                                                                     
                                                                                          
                                                                                          
U-Boot 2020.01-dirty (Jan 15 2020 - 22:04:24 +0100) Allwinner Technology                  
                                                                                          
CPU:   Allwinner H6 (SUN50I)                                                              
Model: Eachlink H6 Mini                                                                   
DRAM:  2 GiB                                                                              
MMC:   mmc@4020000: 0, mmc@4022000: 1                                                     
Loading Environment from FAT... Unable to use mmc 1:1... In:    serial@5000000            
Out:   serial@5000000                                                                     
Err:   serial@5000000                                                                     
Net:   No ethernet found.
Hit any key to stop autoboot:  0 
...

maybe the axp805 probing should be made optional by some atf compile time option?

a lot of thanks in advance and best wishes - hexdump

No rule to make target 'bl31'.

Hello,

i'm following the instrunction in board/sunxi/README.sunxi64. But they seems to be outdated. They say to use "allwinner" branch, but I don't find it. And if I run this command:

make PLAT=sun50iw1p1 DEBUG=1 bl31

It gives me an error: "no rule to make target bl31".

Thanks.

Question about using lpdd3/ddr4 on h616！

We want to use lpddr/ddr4 on h616, but the mainline u-boot does not support it, is there any other way than using sunxi-uboot?