Networking for the AJIT Processor
code : Contains all design files
build : All test and build scripts
docs : Documentation of Design and components
boards : All resources required to implement on vc709 fpga card
10G_MAC_Core : Top-Level RTL of 10G Xilinx MAC IP with interfaces to custom AHIR FIFOs
Tri-Mode MAC_Core : Top Level RTL of Tri-Mode Xilinx MAC IP (Coming soon...)