ataradov/riscv

Verilog implementation of a RISC-V core

riscv's Issues

unable to pass testsuite

Hi,

I'm currently trying (as a sanity check) to pass the test suite you provided.

I used both my own compiled risc-v toolchain as well as the centos binary distribution of the eclipse mcu tools you've been using in the makefile. Result is the same.

In both cases, the test errors out at the signed division (Just ran the divider in this case):

make all
WARNING: memory.v:106: $readmemh(../firmware/test.mem): Not enough words in the file for the requested range [0:2047].
VCD info: dumpfile /tmp/__riscv.vcd opened for output.
------ reset = 1
------ reset = 0

--- main ---

HW/SW divider:
i = 0
i = 1
Assertion failed: Signed divide error (Q): 00000001 / ffffffff: sw = 00000000, hw = ffffffff

*** halting ***

--- HALT (51566 cycles) ---

Any hints on this? Am I missing something?

auipc instruction broken

Hi!

I have played with the core a little more and I have discovered that the AUIPC instruction seems to miscalculate its target address because it takes a register value instead of the PC.

I discovered this while compiling a bit more elaborate application which uses this. I have not seen this instruction being built in by the compiler with your test code, which might by why that issue slipped through.

I was working on a fix and one way to do it might be: to change one assignment in the instrcution decode pipe (line 562):

id_ra_value_r <= auipc_w ? if_pc_r : reg_r[id_ra_index_w];

What do you think?

is Multiplier right work in riscv_core.v?

/- Multiplier --------------------------------------------------------------/
`ifdef USE_NATIVE_MULTIPLIER
wire [63:0] mul_opa_a_w = { {32{id_a_signed_r & id_ra_value_r[31]}}, id_ra_value_r };
wire [63:0] mul_opa_b_w = { {32{id_b_signed_r & id_rb_value_r[31]}}, id_rb_value_r };
wire [63:0] mul_res_w = mul_opa_a_w * mul_opa_b_w;
wire ex_stall_mul_w = 1'b0;

`else // Slow sequntial multiplier
reg mul_busy_r;
reg mul_ready_r;
reg [4:0] mul_count_r;
reg [63:0] mul_res_r;

wire [32:0] mul_sum_w = { 1'b0, mul_res_r[63:32] } + { 1'b0, mul_res_r[0] ? mul_div_b_w : 32'h0 };

wire [63:0] mul_res_w = mul_div_negative_w ? -mul_res_r : mul_res_r;

always @(posedge clk_i) begin
if (reset_i) begin
mul_busy_r <= 1'b0;
mul_ready_r <= 1'b0;
mul_count_r <= 5'd0;
mul_res_r <= 64'h0;
end else begin
if (mul_busy_r) begin
mul_count_r <= mul_count_r - 5'd1;
mul_res_r <= { mul_sum_w, mul_res_r[31:1] };

  if (mul_count_r == 5'd0) begin
    mul_busy_r  <= 1'b0;
    mul_ready_r <= 1'b1;
  end

end else if (mul_ready_r) begin
  mul_ready_r <= 1'b0;

end else if (mul_request_w) begin
  mul_count_r <= 5'd31;
  mul_busy_r  <= 1'b1;
  mul_res_r   <= { 32'h0, mul_div_a_w };
end

end
end

wire mul_request_w = (ALU_MULL == id_alu_op_r || ALU_MULH == id_alu_op_r);
wire ex_stall_mul_w = mul_request_w && !mul_ready_r;
`endif

I doubt it