awhigham9/inliner

Software suite to pre-process verilog files for automatic test generation by inlining module instantiations

inliner's Issues

Inout Port Support

Add functionality to support the inlining of inout ports in Inliner._instantiation_to_inlined_body.

Redundant Net/Reg Redeclaration

Currently output ports are converted to wire (if the original is just output) or reg (if the original is output reg) during the inlining process in the method Inliner._instantiation_to_inlined_body. This is done through a simple find and replace mechanism. However, this in Verilog it is typical, though not required, to declare and output and a reg of the same name (which hold the same values). For example:

module Foo;
    output bar;
    reg bar;
    //Code
endmodule;

When this is inlined from its instantiation by the aforementioned method, it will have a declaration of a wire bar and reg bar, which is incorrect. Only the latter declaration should be present.

One solution to this could be creating a new data member within the Module object to store a list of all regs and wires within the module. Alternatively a similar check could be performed at the time an output port is converted.

Update Tokenizer and Inliner to Support Most Recent Verilog Standard

Currently, the software supports 1364-2005 - IEEE Standard for Verilog Hardware Description Language. However, the more recent 1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language has superseded this.

We have to identify what needs to be updated, including changes in lexing, token classification, module inlining, etc. After this discovery process we have to implement these changes.

Stress Test inline.py

Run inline.py on large input files to test the viability of the software in actual applications. This should be done before merging develop into master.

Add a Library/API Reference

Add a reference for major functions and modules within the software suite, including purpose, parameters, return values, etc. This can be its own markdown file or part of README.md

Missing Semicolons

Currently, some semicolons are lost during the inlining process within the Inliner._instantiation_to_inlined_body method. This most likely occurs in the loops which merge the modified statements with their original versions in the latter half of the method.

Create Executable

Create and push and executable bash script that can run on a group of input files, combine the files into one file, and then run the inlining software.

In-Port-List Port Declarations Handled Incorrectly

If ports are declared in the module port list instead of within the module body, they are not handled correctly. To provide an example, for the following two verilog modules, the first will not be processed correctly, while the second will.

module mod1(
    input data_in,
    output data_out
);
    //Code
endmodule

module mod2(
    data_in,
    data_out
);
    input data_in;
    output data_out;
    //Code
endmodule

Complete the README

Finish writing and pushing the README for the project.