barefootnetworks/open-tofino

open-tofino's Issues

Recirculating a packet to multiple pipeline

Assume a tofino switch with n pieplines. If we recirculate a packet from a pipeline is it possible to send that recirculated packet to every pipeline?

P4 Tofino Example Programs?

This repository contained quite a few Tofino 1 (or 2) example programs, but they seem to have been removed. Is there a reason for this?

Some Possible Mistakes in PUBLIC_Tofino-Native-Arch.pdf Figure5

Hello, I have read the documentation "PUBLIC_Tofino-Native-Arch.pdf" and found Figure5 quite confusing.

Firstly, since t1 and t3 share the same Action Spec in Table(a), may be they should share the same Action Spec in Table(b) too?

Also, in "For Table(b)", I think there should be only two raws "m1 set_port(1)" and "m2 set_port(2)".

Please check these details carefully. Thank you!

Where can I find the application note on Tofino2 as pubulished in document, "P416 Intel® Tofino™ Native Architecture – Public Version".

I found a document on tofino 1 native architecture, which is
P416 Intel® Tofino™ Native Architecture – Public Version.
However, how could we access to the document on tofino 2? Whether there is some restriction to access it? Could you please tell us?
Thanks a lot.

including bfruntime.proto file

Hi,
it would be great if the bfruntime.proto file would be open sourced as well in this repository. By that, control plane apps can be programmed in any language, i.e. in our case Golang and Python, and open sourced. As the C header files for the API are already in this reposity, I don't assume any new confidential content in there.

Our current workaround (which is very ugly) is: 1. we provide the Golang/Python code without the bfruntime.proto file, 2. the user has to find the proto file in the sde and copy it into the project and 3. compile the proto file with the protobuf compiler by himself.
--> This would be much easier if the proto file is public available.

best,
Ralf

Why were some of Open Tofino projects removed from README.md

I found some of projects using Open Tofino in ongoing research: has been removed from README.md when merging updates of SDE9.9.0 with this commit: 2c83863

But I still find the removed link published as before. e.g. https://github.com/SIDN/p4-scion

Was this intentional? If so, what was the criteria of removing them. (Just from curiosity)

How can I shift data in register?

I have trouble when compiling my p4 program in tna. I want to left-shift data and write the result into the register. But I got the error information: "expression too complex for register action: reg_data = reg_data << LEFT_SHIFT;"

deq_timedelta

Hi,

Considering that enq_tstamp/global_timestamp is in ns I would assume the the deq_timedelta also in ns and not us, is this correct?
I can recall something about reading (all) the timestamps being in ns but I can't seem to find it anymore, so I want to be sure :). I checked the p4include/tofino.p4 file and and the pdf but I could not find it stated there.
So it would range from 1 ns to approximately 262 us.

SDE9.2.0: use API got "$pre.node : Value 16 is greater than what field size 4 for field id 1 allows" errors

When I use the API "BfRtTableKey->setValue" to add entries, when the key value is big then 15, there will throw out the error msg: "$pre.node : Value 16 is greater than what field size 4 for field id 1 allows".
I have checkout that the key size of the table "$pre.node" is 32bits. Why I got this error? How can I add entry for this table correctly? Or it's bug for the version 9.2.0?

Does tofino2 have some functions that tofino does not have?

Hello, I checked the contents of the tofino.p4 and tofino2.p4 files and found that there is no adv_flow_control field in the ingress_intrinsic_metadata_for_deparser_t section in the tofino architecture, while the tofino2 architecture contains this field. Does this mean that the advanced flow control function can only be used in tofino2?

How many TCAM entries are consumed by one range？

Please be aware that the implementation of range match consumes multiple TCAM entries per range entry and refer to the documentation for details.

How many TCAM entries are consumed by one range？
Where can the documentation be found?

Adding multicast node entry into the multicast group table with turned off pruning but same L1_XID among multiple entries

Hello I would like to ask you on this paragraph from the PDF document on page 28:

Does it mean that regardless I use or don't use prunning, then every multicast node entry(bfrt.pre.node) in the multicast group table (bfrt.pre.mgid) MUST have assigned L1_XID?

Second question, L1_XID must be unique for every entry?

Example, what will happen if I create two multicast nodes with different Level 1 node ID and then add them into the same multicast group table with the same L1_XID = 0 and MULTICAST_NODE_L1_XID_VALID = False (using False because it was used in the Intel Networking Academy labs example - possible mistake in the scripts for solution of the labs)?

My guess is that L1_XID must be unique among entries in one table and it doesn't matter if prunning is turned on or turned off.

License Is Not Compatible With Open Source

The repository is licensed as CC-BY-ND-4.0. Despite CC licenses not being intended for use with code, the fact that this license is used means that it is not compatible with open source. Taking the worst-case view (which one must), any adaptation, transformation, or anything that is builds upon this work cannot be shared. This would include executables or P4 programs including any of the headers, and I would then not be able to create an open source helper library based upon the protobuf definition requested in #10 (which I intended on doing).

Given the name of the repository, I was wondering whether this was an oversight? Would you consider re-licensing under GPL or Apache (The p4.org philosophy appears to abhor GPL)?

Is opening up Tofino still on the table?

Given Intel's pause on Tofino, is this project of gradually opening tofino still happening? Is there any published timeline?

"tna_32q_2pipe" for 2 pipes switch

Hi,
I'm trying to run the example "tna_32q_2pipe" and when I execute the ./run_switchd.sh --arch tofino -p tna_32q_2pipe I get some errors:

2022-03-03 21:55:27.055651 BF_DVM ERROR - Program "tna_32q_2pipe" Pipeline "pipeline_profile_a" cannot be assigned to device 0 pipe 2, only 2 pipe(s) available
2022-03-03 21:55:27.055722 BF_DVM ERROR - Program "tna_32q_2pipe" Pipeline "pipeline_profile_b" cannot be assigned to device 0 pipe 3, only 2 pipe(s) available
ERROR: bf_device_add failed(3) for dev_id 0
ERROR: bf_switchd_device_add failed(3) for dev_id 0

and there are no ports to show up

bf-sde.pm> show -a
-----+---2022-03-03 21:53:37.775510 BF_PM ERROR - pm_port_info_get_first:191 Unable to get first port info for dev : 0, port_key 140474654489680 : map_err : 2
-+---+----+-------+----+---+---+---+--------+----------------+----------------+-
PORT |MAC |D_P|P/PT|SPEED  |FEC |RDY|ADM|OPR|LPBK    |FRAMES RX       |FRAMES TX       |E
-----+----+---+----+-------+----+---+---+---+--------+----------------+----------------+-

I'd like to know how to fix this problem？Thanks😊

Can global registers be implemented？

I want to make deq_qdepth (from egress_intrinsic_metadata_t) available in the SwitchIngress. So I try to declare a global Register, and the same register will be used by RegisterAction defined in SwitchIngress and SwitchEgress. In this way, the data can be shared between SwitchIngress and SwitchEgress.

The p4 code looks like:

Register<T, I>(size, initial_value) global_reg;

control SwitchIngress(...) {
    RegisterAction<T, I, U>(global_reg) global_reg_action1 = {...};
    
    apply {
        ...;
        global_reg_action1.execute(idx);
    }
}

control SwitchEgress(...) {
    RegisterAction<T, I, U>(global_reg) global_reg_action2= {...};

    apply {
        ...;
        global_reg_action2.execute(idx);
    }
}

However, it seems like impossible to implement.

I wonder if there is any approach to achieve this "global register"? Thanks a lot.

execute test.py of tna_timestamp, I have some issue

Execute test.py of nta_timestamp, there are the following issues

root@lanner-control:~/bf-sde-9.5.0# ./run_p4_tests.sh -p tna_timestamp
Using SDE /root/bf-sde-9.5.0
Using SDE_INSTALL /root/bf-sde-9.5.0/install
Using TEST_DIR /root/bf-sde-9.5.0/pkgsrc/p4-examples/p4_16_programs/tna_timestamp
Using PATH /root/bf-sde-9.5.0/install/bin:/root/bf-sde-9.5.0/install/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
Arch is tofino
Target is asic-model
Using BF_PTF with bf_pktpy.
Setting up veth interfaces
No of Veths is 64
Adding CPU veth
Connecting to localhost port 7777 to check status on these devices: [0]
Waiting for device 0 to be ready
Started port clean script
: <type 'str'>
/root/bf-sde-9.5.0/install/lib/python2.7/site-packages/bf-ptf:/root/bf-sde-9.5.0/install/lib/python2.7/site-packages/p4testutils:/root/bf-sde-9.5.0/install/lib/python2.7/site-packages/tofinopd/:/root/bf-sde-9.5.0/install/lib/python2.7/site-packages/tofino:/root/bf-sde-9.5.0/install/lib/python2.7/site-packages/: <type 'str'>
test.TimestampTest ... Subscribe attempt #1
Subscribe response received 0
Binding with p4_name tna_timestamp
Binding with p4_name tna_timestamp successful!!
Received tna_timestamp on GetForwarding on client 0, device 0
ERROR

======================================================================
ERROR: test.TimestampTest

Traceback (most recent call last):
File "/root/bf-sde-9.5.0/pkgsrc/p4-examples/p4_16_programs/tna_timestamp/test.py", line 73, in runTest
nrcv = ipkt.class(rcv_pkt)
TypeError: init() takes exactly 1 argument (2 given)

---

Ran 1 test in 2.203s

FAILED (errors=1)
()

---

ATTENTION: SOME TESTS DID NOT PASS!!!
()
The following tests errored:
TimestampTest
()

---

P4 Compiler

Is there any P4 compiler available (as open-source) for this switch?

register support write operation?

Does the register in P4_16 support write opreration ? Could you give an example of register write operation in P4_16?

Coherency in Register values when Identical P4 code is used for all pipes?

In the, "Identical P4 code for all pipes " section the specs say, identical code is executed on all the pipes? Now if the P4 code contains access to register-based stateful memory, does Tofino maintains coherency among the register values across the pipes?

Can an Indirect Register array spread across over multiple stages? I am mainly interested to know how many flowlet information I can maintain in a register array. Is this number bounded by the SRAM available in each stage?