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0.0 1.0 0.0 416.02 MB

Makefile 0.02% C 1.51% Groff 0.01% HTML 0.25% Verilog 20.06% Tcl 0.09% JavaScript 0.07% Shell 0.04% Batchfile 0.01% SuperCollider 0.02% C++ 0.08% Assembly 0.04% CartoCSS 0.01% VHDL 75.44% Coq 2.13% SystemVerilog 0.16% Stata 0.01% TeX 0.06% CSS 0.01% Perl 0.01%

kc705_dds's Introduction

VHDL_DDS

To Run on KC705 with FMC150 A/D Daughter Card:

Copy "k7dsp_rtl_tut_sp_edit_v2/" folder to c:/

Set GPIO 2,3,4 switches to zero and GPIO switch 1 to one.

Vivado Project File Location :

k7dsp_rtl_tut_sp_edit_v2/k7dsp_rtl_tut/RTL/RefDes/imp/VHDL/Vivado

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