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License: Other
Register map generator for VHDL digital designs and Embedded Systems.
License: Other
This is problem because basic level of Intel Quartus provides only partial support for VHDL 2008.
Full support is available only in paid PRO tools. Xilinx Vivado (as of 2018 version) supports
required features of VHDL 2008 but wne code is used in component then VHDL 2008
attribute cannot be passed from IP Package Editor to main project.
File templates/memory_reg.vhd causes nex error in Quartus
"generic data_width cannot be used in its own interface list"
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