A template project for testing Verilog/ Systemverilog designs using Verilator and Doctest
TODO: Expand readme with setup notes
REQUIREMENTS: verilator: Verilog HDL simulator for cycle accurate verification. https://www.veripool.org/wiki/verilator gtkwave: Open source GTK+ based waveform viewer. http://gtkwave.sourceforge.net/ doctest: Fast C++98/C++11 single-header test framework. https://github.com/onqtam/Doctest g++: GNU C++ compiler
OPTIONAL: These are some optional prgrams that can be used to generate some useful test structures. indent: GNU C formatter. https://www.gnu.org/software/indent/ python 3: bdp: Python module for generating Tikz block diagrams. https://pypi.python.org/pypi/bdp/0.2