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Code to write/burn data to the RC2014 512k ROM 512k RAM board

Home Page: http://bread80.com/?p=153

License: MIT License

Assembly 100.00%
z80 rc2014 hardware assembler norflash software-overwrite-protection eeprom memory

rc2014-512k-rom-512k-ram-board's Introduction

512k-rom-512k-ram

Code to write data to the ROM on the RC2014 official 512K ROM 512K RAM module using a Z80 processor

For full background and explanation see: http://bread80.com/?p=153

This code probably works with other similar modules but hasn't been tested with other hardware. Specifically this code is writing to the SST39SF040 NOR flash IC. It may work with other chips which use software write protection.

Originally written by Mike Sutton - Bread80.com Licenced under the MIT licence

The first section is some test routines which may be useful but you'll have to use the symbol table or disassembler to find the entry addresses (sorry). Change the include_test_code constant to assemble without them.

Written and tested with the RASM assembler

Files: NORflash.asm - The Z80 Assember source rasmoutput.bin - Raw binary output from the assembler output.hex - Hex file version of the output

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gallegux

rc2014-512k-rom-512k-ram-board's Issues

Suggestion to article about 512k ROM 512k RAM Board

Hi!

Thanks for the article Understanding the RC2014 512k ROM 512k RAM Board!
In the article you write:

There’s also one more port, $7c, which is used to enable (value 1) or disable (value 0) the banking mechanism. With the banking mechanism disabled logical banks 0 to 3 map directly to physical banks 0 to 3 which, you’ll remember, are ROM. This is important mechanism at boot up: the banking mechanism is disabled at reset, physical ROM banks $00 to $03 are paged in and the Z80 begins by executing boot code in physical ROM bank $00. (And this code will, if it has any sense, begin by mapping in some RAM so that it has a stack available if not an area for data storage).

I didn't find any logic which maps logical banks 0 to 3 to physical ROM banks 0 to 3 at reset.
From what I see, at reset (e.g. when 74xx670 outputs are disabled) every logical bank (0-3) is mapped to a physical ROM bank 0 (CPU lines A14 and A15 are just ignored, MA14 and MA15 are pulled down by default).

It may be the case that I misunderstood something, so I kindly ask you to revise the article.

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