candecoder's People
candecoder's Issues
Misuse of clock domains
I have learned a lot about FPGAs since writing this decoder
The modules here make extensive use of blocks clocked at edges derived from logic. - this is bad practice.
This allows clock skew to build up between logic blocks, likely resulting in hard-to-debug glitches downstream, and makes the optimiser work very hard trying to figure out what can really be a physical clock domain, and what should be demoted to ordinary conditional synchronous logic
The use of compact testable logic blocks still seems sane, and the one-hot state-machine decoder is a powerful approach for this protocol (allows lower latency reactions than shift-register packet-based decode)
I'm leaving this repo up because there's precious little on the web about hardware CAN decoders, but please be aware that the code itself needs a lot of style changes before it'll behave in a larger codebase, and the enumeration of states in these files might save someone time if they ever chose to build their own one-hot decoder
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