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undefined reference to `get_model_port'

What steps will reproduce the problem?
1. in libvpr_5: make clean && make
2. in odin_II: make clean && make 
3.

What is the expected output? What do you see instead?
OBJ/memories.o: In function `pad_memory_input_port':
../SRC/memories.c:1467: undefined reference to `get_model_port'
OBJ/memories.o: In function `pad_memory_output_port':
../SRC/memories.c:1426: undefined reference to `get_model_port'
OBJ/memories.o: In function `split_dp_memory_to_arch_width':
../SRC/memories.c:1109: undefined reference to `get_model_port'
OBJ/memories.o: In function `split_sp_memory_to_arch_width':
../SRC/memories.c:990: undefined reference to `get_model_port'

What version of the product are you using? On what operating system?
Starting from r231, in vpr5 build mode. 
Running on Red Hat Enterprise Linux Server release 5.

Please provide any additional information below.


Original issue reported on code.google.com by [email protected] on 23 Dec 2011 at 8:56

read_blif arguments incorrect

What steps will reproduce the problem?
1. make clean && make
2.
3.

What is the expected output? What do you see instead?
SRC/odin_ii.c:332: error: too many arguments to function read_blif
SRC/odin_ii.c:332: error: void value not ignored as it ought to be


What version of the product are you using? On what operating system?
Downloaded source usin: svn checkout http://odin-ii.googlecode.com/svn/trunk/ 
odin-ii-read-only today (9/27/2011)
Running on Ubuntu.

Please provide any additional information below.
in file odin_ii.c, read_blif is called:
   blif_netlist = read_blif (global_args.activation_blif_file, lut_size);

in file read_blif.c, the function is defined as:
   void read_blif(char * blif_file)



Original issue reported on code.google.com by [email protected] on 27 Sep 2011 at 11:33

Some Verilog constructs are giving error while running ODIN

What steps will reproduce the problem?
1. I have downloaded VTR 7.0 release.

2. My design is in verilog.

3. Running ODIN II for my verilog design is giving error for the constructs in 
the verilog file. I have mentioned these constructs in next point.

4. I am using following verilog constructs in the design:
       (a) 
                input wire portname1;
                output wire portname2;

       (b)      output reg portname;

       (c)  It is giving error for any operation while binding ports of 
            the instance of child module:

             clock_gating  instanceNmae(.clock_enable(disable_cen_clk | cen_inst1));

       (d) genvar/generate constructs of verilog are giving error.

       (e) Following statement is giving error:
               wire x1x2 = x[0] ^ x[1];

       (f) “signed” and ”unsigned” constructs are giving error in ODIN.  
           Example is:
             wire signed [15:0] var1;
             reg signed [15:0] var2;

       (g) We know that in the release note of the ODIN II it was mentioned that "parameter" is not supported by ODIN. So, That limitation still holds or it is not there in the new code?

       (h) Following statement is giving error:
            int_counter <= 7'b000_0000;


I am using Linux CentOs 7.0.


Please replies asap.

Thanks
Ramesh

Original issue reported on code.google.com by [email protected] on 14 May 2015 at 6:46

munmap segmentation fault

What steps will reproduce the problem?
1. Configure the makefile of odinII in VPR5 mode 
2. run odinII in the power estimation flow for activation estimation with the 
files provided in "VPR 5.0 with Power Estimation"
-B diffeq.map4.latren.blif
-N diffeq.4.10.net
-a k4-n10pow_uni.xml
3.

What is the expected output? What do you see instead?
Segmentation fault

What version of the product are you using? On what operating system?
I downloaded on Friday. I believe it is r226.

Please provide any additional information below.
Attached file is the strace output.
There seems to be a problem with munmap.

Original issue reported on code.google.com by [email protected] on 12 Dec 2011 at 8:27

Attachments:

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